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R32C/111 Group Datasheet
PRELIMINARY
R32C/111 Group
RENESAS MCU
REJ03B0227-0030 Rev.0.30 Aug 19, 2008
1.
1.1
Overview
Features
The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral functions, provides support for a vast range of application fields. The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture, multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of onchip peripheral devices -- UART, CRC, DMAC, A/D and D/A converters, timers, I2C, and WDT enables to minimize external components. The R32C/100 Series, in particular, provides the R32C/111 Group as a standard product. This product, provided as 100-pin plastic molded LQFP package, configures nine channels of serial interface.
1.1.1
Applications
Audio, cameras, television, home appliance, printer, meter, office/industrial equipment, communication/ portable devices
Notes to users:
* While the information contained herein is believed to be accurate, it may contain technical inaccuracies or typographical errors. * Specifications may be subject to change due to product improvements or other reasons. Please verify the document is the latest version available.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 1 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
1.1.2
Performance Overview
Table 1.1 and Table 1.2 show the performance overview of the R32C/111 Group. Table 1.1 Unit CPU R32C/111 Group Performance (1/2) Function Central processing unit Performance R32C/100 Series CPU Core * Basic instructions: 108 * Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz) * Multiplier: 32-bit x 32-bit 64-bit * Multiply-accumulate unit: 32-bit x 32-bit + 64-bit 64-bit * IEEE-754 floating point standard: Single precision * 32-bit barrel shifter * Operating mode: Single-chip mode, memory expansion mode, microprocessor mode (optional (1)) Flash memory: 256 to 512 Kbytes RAM: 40 to 63 Kbytes Data flash: 4 Kbytes x 2 blocks Refer to Table 1.3 for memory size of each product group Bus and memory expansion * Address space: 4 Gbytes (available up to 64 Mbytes) * External bus Interface: Support for wait-state insertion, 4 chip select outputs, 3V/5V interface * Bus format: Separate bus/Multiplexed bus selectable, data bus width selectable (8/16 bits) Optional (1) Low voltage detection interrupt * 4 circuits (main clock, sub clock, PLL, on-chip oscillator) * Oscillation stop detector: Main clock oscillator stop/re-oscillation detection * Frequency divide circuit: Divide-by-2 to divide-by-24 selectable * Low power modes: Wait mode, stop mode Interrupt vectors: 261 External interrupt inputs: NMI, INT x 6, key input x 4 Interrupt priority levels: 7 levels 15 bits x 1 (selectable input frequency from prescaler output) 4 channels * Cycle-steal transfer mode * Request sources: 51 * 2 transfer modes: Single transfer, repeat transfer * Can be activated by any peripheral interrupt source * 3 transfer functions: Immediate data transfer, calculation transfer, chained transfer * 2 input-only ports * 82 CMOS inputs/outputs * 2 N-channel open drain ports * A pull-up resistor is selectable for every 4 input ports DMAC
Memory
External Bus Expansion
Voltage Detector Clock
Low voltage detector Clock generator
Interrupts
Watchdog Timer DMA
DMAC II
I/O Ports
Programmable I/O ports
Note: 1. Please contact a Renesas sales office to use the optional feature.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 2 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
Table 1.2 Unit Timer
R32C/111 Group Performance (2/2) Function Timer A Performance 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Two-phase pulse signal processing in event counter mode (twophase encoder input) x 3 16-bit timer x 6 Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode Three-phase motor control timer x1 (timers A1, A2, A4, and B2 used) 8-bit programmable dead time timer
Timer B
Three-phase motor control timer Serial Interface
UART0 to UART8 Asynchronous/synchronous serial interface x 9 channels * I2C-bus (UART0 to UART6) * Special mode 2 (UART0 to UART6) * IEBus (1) (optional (2)) (UART0 to UART6) 10-bit resolution x 26 channels Sample & hold functionality integrated 8-bit resolution x 2 CRC-CCITT (X16 + X12 + X5 + 1) 16 bits x 16 bits Time measurement (input capture): 16 bits x 16 Waveform generation (output compare): 16 bits x 19 Serial interface: Variable-length synchronous serial I/O mode, IEBus (1) mode Programming and erasure supply voltage: VCC1 = VCC2 =3.0 to 5.5 V Minimum endurance: 1, 000 erase/program cycles Read protection: ROM code protect, ID code check Debugging: On-chip debug, on-board flash reprogramming 50 MHz/VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 V to VCC1 -20C to 85C (version N) -40C to 85C (version D) 32 mA (VCC1 = VCC2 = 5.0 V, f(CPU) = 50 MHz) 8 A (VCC1 = VCC2 = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode) 100-pin plastic molded LQFP (PLQP0100KB-A)
A/D Converter D/A Converter CRC Calculator X-Y Converter Intelligent I/O
Flash Memory
Operating Frequency/Supply Voltage Operating Temperature Current Consumption Package
Notes: 1. IEBus is a trademark of NEC Electronics Corporation. 2. Please contact a Renesas sales office to use the optional feature.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 3 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
1.2
Product Information
Table 1.3 lists the product information and Figure 1.1 shows the details of the part number. Table 1.3
R5F64110NFB R5F64110DFB R5F64111NFB R5F64111DFB R5F64112NFB R5F64112DFB R5F64114NFB R5F64114DFB R5F64115NFB R5F64115DFB R5F64116NFB R5F64116DFB
R32C/111 Group Product List
Package Code (1) ROM Capacity (2) RAM Capacity (P) (D) (P) (D) (P) (D) (P) (D) (P) (D) (P) (D) PLQP0100KB-A 256 Kbytes +8 Kbytes 384 Kbytes +8 Kbytes 512 Kbytes +8 Kbytes 40 Kbytes 256 Kbytes +8 Kbyts 384 Kbytes +8 Kbytes 512 Kbytes +8 Kbytes 63 Kbytes
As of August, 2008
Remarks -20C to 85C (version N) -40C to 85C (version D) -20C to 85C (version N) -40C to 85C (version D) -20C to 85C (version N) -40C to 85C (version D) -20C to 85C (version N) -40C to 85C (version D) -20C to 85C (version N) -40C to 85C (version D) -20C to 85C (version N) -40C to 85C (version D)
Part Number
(D): Under development (P): On planning phase
Notes: 1. The old package code is as follows: PLQP0100KB-A: 100P6Q-A 2. Data flash memory provides an additional 8 Kbytes of ROM capacity.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 4 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
Part Number R5 F 64 11 6 N -XXX FB
Package Code FB : PLQP0100KB-A ROM Number Omitted in the flash memory version Temperature Code N : -20C to 85C D : -40C to 85C ROM/RAM Capacity 0 : 256 KB/63 KB 1 : 384 KB/63 KB 2 : 512 KB/63 KB 4 : 256 KB/40 KB 5 : 384 KB/40 KB 6 : 512 KB/40 KB R32C/111 Group R32C/100 Series Memory Type F : Flash memory version
Figure 1.1
Part Numbering of Product
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 5 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows s block diagram of the R32C/111 Group.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
VCC2 Peripheral functions Timer:
Timer A Timer B 16 bits x 5 timers 16 bits x 6 timers
VCC1
Port P7
8
A/D converter:
10 bits x 1 circuit Standard: 10 inputs Maximum: 26 inputs
Clock generator:
4 circuits - XIN-XOUT - XCIN-XCOUT - On-chip oscillator - PLL frequency synthesizer
Port P8
7
Three-phase motor controller Serial interface:
9 channels
D/A converter:
8 bits x 2 channels
P8_5
DMAC Watchdog timer:
15 bits
VCC1
X-Y converter:
16 bits x 16 bits
DMAC II Memory ROM RAM Multiplier Floating-point unit
P9_1
CRC calculator (CCITT)
X +X +X +1
16 12 5
R32C/100 Series CPU Core
R2R0 R2R0 R3R1 R3R1 R6R4 R6R4 R7R5 R7R5 A0 A0 A1 A1 A2 A2 A3 A3 FB FB SB SB FLG INTB ISP USP PC SVF SVP VCT
Port P9
Intelligent I/O
Time measurement: 16 Wave generation: 19 Serial interface: - Variable-length synchronous serial I/O - IEBus (1)
5
Port P10
8
Note: 1. IEBus is a trademark of NEC Electronics Corporation.
Figure 1.2
R32C/111 Group Block Diagram
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 6 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
1.4
Pin Assignments
Figure 1.3 shows the pin assignments (top view) and Table 1.4 to Table 1.6 show the pin characteristics.
(Note 1)
P1_3 / D11 / IIO0_3 / IIO1_3 P1_4 / D12 / IIO0_4 / IIO1_4 P1_5 / D13 / INT3 / IIO0_5 / IIO1_5 P1_6 / D14 / INT4 / IIO0_6 / IIO1_6 P1_7 / D15 / INT5 / IIO0_7 / IIO1_7 P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0 P2_1 / A1 / [A1/D1] / AN2_1 P2_2 / A2 / [A2/D2] / AN2_2 P2_3 / A3 / [A3/D3] / AN2_3 P2_4 / A4 / [A4/D4] / AN2_4 P2_5 / A5 / [A5/D5] / AN2_5 P2_6 / A6 / [A6/D6] / AN2_6 P2_7 / A7 / [A7/D7] / AN2_7 VSS P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A VCC2 P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B P3_2 / A10 / [A10/D10] / TA1OUT / V P3_3 / A11 / [A11/D11] / TA1IN / V P3_4 / A12 / [A12/D12] / TA2OUT / W P3_5 / A13 / [A13/D13] / TA2IN / W P3_6 / A14 / [A14/D14] / TA4OUT / U P3_7 / A15 / [A15/D15] / TA4IN / U P4_0 / A16 / CTS3 / RTS3 / SS3 P4_1 / A17 / CLK3
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
IIO0_2 / IIO1_2 / D10 / P1_2 IIO0_1 / IIO1_1 / D9 / P1_1 IIO0_0 / IIO1_0 / D8 / P1_0 AN0_7 / D7 / P0_7 AN0_6 / D6 / P0_6 AN0_5 / D5 / P0_5 AN0_4 / D4 / P0_4 AN0_3 / D3 / P0_3 AN0_2 / D2 / P0_2 AN0_1 / D1 / P0_1 AN0_0 / D0 / P0_0 KI3 / AN_7 / P10_7 KI2 / AN_6 / P10_6 KI1 / AN_5 / P10_5 KI0 / AN_4 / P10_4 AN_3 / P10_3 AN_2 / P10_2 AN_1 / P10_1 AVSS AN_0 / P10_0 VREF AVCC STXD4 / SCL4 / RXD4 / ADTRG / P9_7 SRXD4 / SDA4 / TXD4 / ANEX1 / P9_6 CLK4 / ANEX0 / P9_5
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50
VCC2
49 48 47 46 45 44 43
R32C/111 GROUP
PLQP0100KB-A (100P6Q-A) (Top view)
42 41 40 39 38 37 36 35 34 33 32 31 30 29
VCC1
1 2 3 4 5 6 7 8 9
28 27 26
P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6 P4_5 / CS2 / A21 / CLK6 P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6 P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6 P5_0 / WR0 / WR P5_1 / WR1 / BC1 P5_2 / RD R5_3 / CLKOUT / BCLK P5_4 / HLDA / CS1 / TXD7 P5_5 / HOLD / CLK7 P5_6 / ALE / CS2 / RXD7 P5_7 / RDY / CS3 / CTS7 / RTS7 P6_0 / TB0IN / CTS0 / RTS0 / SS0 P6_1 / TB1IN / CLK0 P6_2 / TB2IN / RXD0 / SCL0 / STXD0 P6_3 / TXD0 / SDA0 / SRXD0 P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 P6_5 / CLK1 P6_6 / RXD1 / SCL1 / STXD1 P6_7 / TXD1 / SDA1 / SRXD1 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT (Note 3) P7_1 / TB5IN / TA0IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN (Note 3) P7_2 / TA1OUT / V / CLK2
(Note 2)
Notes: 1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins. 2. The position of pin number 1 varies by product. Refer to the index mark attached "Package Dimensions". 3. P7_0 and P7_1 as output are open drain outputs.
Figure 1.3
Pin Assignment (top view)
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 7 of 81
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P9_4 TB3IN / DA0 / P9_3 VDC0 P9_1 VDC1 NSD CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC1 NMI / P8_5 INT2 / P8_4 INT1 / P8_3 INT0 / P8_2 UD0B / UD1B / IIO1_5 / RTS5 / CTS5 / SS5 / U / TA4IN / P8_1 UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0 UD0B / UD1B / IIO1_4 / CLK5 / TA3IN / P7_7 UD0A / UD1A / IIO1_3 / RTS8 / CTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6 IIO1_2 / RXD8 / W / TA2IN / P7_5 IIO1_1 / CLK8 / W / TA2OUT / P7_4 IIO1_0 / TXD8 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
Table 1.4
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VDC1 NSD CNVSS XCIN RESET XOUT VSS XIN VCC1 VDC0 Control Pin
Pin Characteristics (1/3)
Port P9_4 P9_3 P9_1 Interrupt Pin Timer Pin TB4IN TB3IN UART Pin CTS4/RTS4/SS4 Intelligent I/O Pin Analog Pin DA1 DA0 Bus Control Pin
P8_7
XCOUT P8_6
P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6
NMI INT2 INT1 INT0 TA4IN/U TA3IN TA3OUT TA2IN/W TA1IN/V TB5IN/ TA0IN TA0OUT CTS5/RTS5/SS5 CLK5 TXD5/SDA5/SRXD5/ CTS8/RTS8 RXD8 IIO1_5/UD0B/UD1B UD0A/UD1A IIO1_4/UD0B/UD1B IIO1_3/UD0A/UD1A IIO1_2 IIO1_1 TA4OUT/U RXD5/SCL5/STXD5
TA2OUT/W CLK8 TA1OUT/V CLK2 RXD2/SCL2/STXD2 TXD2/SDA2/SRXD2 TXD1/SDA1/SRXD1 RXD1/SCL1/STXD1 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0 TB2IN TB1IN TB0IN RXD0/SCL0/STXD0 CLK0 CTS0/RTS0/SS0 CTS7/RTS7 RXD7
CTS2/RTS2/SS2/TXD8 IIO1_0 IIO1_7/OUTC2_2/ ISRXD2/IEIN IIO1_6/OUTC2_0/ ISTXD2/IEOUT
OUTC2_1/ISCLK2
RDY/CS3 ALE/CS2
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 8 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
Table 1.5
Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 VSS VCC2 Control Pin
Pin Characteristics (2/3)
Port P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 INT5 INT4 INT3 IIO0_7/IIO1_7 IIO0_6/IIO1_6 IIO0_5/IIO1_5 IIO0_4/IIO1_4 IIO0_3/IIO1_3 TA4IN/U TA4OUT/U TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA3OUT TA0OUT UD0B/UD1B UD0A/UD1A AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 TXD6/SDA6/SRXD6 RXD6/SCL6/STXD6 CLK6 CTS6/RTS6/SS6 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3 CTS3/RTS3/SS3 OUTC2_0/ISTXD2/ IEOUT ISRXD2/IEIN Interrupt Pin Timer Pin CLK7 TXD7 UART Pin Intelligent I/O Pin Analog Pin Bus Control Pin HOLD HLDA/CS1 CLKOUT/ BCLK RD WR1/BC1 WR0/WR CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19 A18 A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) A8(/D8) A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0)/ BC0(/D0) D15 D14 D13 D12 D11
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 9 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
Table 1.6
Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VREF AVCC AVSS Control Pin
Pin Characteristics (3/3)
Port P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 KI3 P10_6 KI2 P10_5 KI1 P10_4 KI0 P10_3 P10_2 P10_1 P10_0 Interrupt Pin Timer Pin UART Pin Intelligent I/O Pin IIO0_2/IIO1_2 IIO0_1/IIO1_1 IIO0_0/IIO1_0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 Analog Pin Bus Control Pin D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
P9_7 P9_6 P9_5
RXD4/SCL4/STXD4 TXD4/SDA4/SRXD4 CLK4
ADTRG ANEX1 ANEX0
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 10 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
1.5
Pin Definitions and Functions
Table 1.7 to Table 1.10 show the pin definitions and functions.
Table 1.7 Pin Definitions and Functions (1/4)
Function Power supply Connecting pins for decoupling capacitor Analog power supply Reset input CNVSS Debug port
Symbol VCC1, VCC2, VSS VDC0, VDC1
I/O I
Power Supply --
Description Applicable as follows: VCC1 and VCC2 = 3.0 to 5.5 V (VCC1 VCC2), VSS = 0 V A decoupling capacitor for internal voltage should be connected between VDC0 and VDC1 Power supply for the A/D converter. AVCC and AVSS should be connected to VCC1 and VSS, respectively The MCU is reset when this pin is driven low This pin should be connected to VSS via a resistor This pin is to communicate with a debugger. It should be connected to VCC1 via a resistor of 1 to 4.7 k Input/output for the main clock oscillator. A ceramic resonator or a crystal oscillator should be connected between pins XIN and XOUT. An external clock should be input at the XIN while leaving the XOUT open Input/output for the sub clock oscillator. A crystal oscillator should be connected between pins XCIN and XCOUT. An external clock should be input at the XCIN while leaving the XCOUT open BCLK output Output of the clock with the same frequency as fC, f8, or f32 Input for external interrupts Input for NMI Input for the key input interrupt Input/output of data (D0 to D7) while accessing an external memory space with a separate bus Input/output of data (D8 to D15) while accessing an external memory space with 16-bit separate bus Output of address bits A0 to A23
-- AVCC, AVSS I
RESET
--
VCC1 VCC1 VCC1 VCC1
I I I/O
CNVSS NSD
Main clock input
XIN
I O
VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC2
Main clock output XOUT
Sub clock input Sub clock output BCLK output Clock output
XCIN XCOUT BCLK CLKOUT
I O O O I I I I/O
External interrupt INT0 to INT5 input NMI input Bus control pins P8_5/NMI D0 to D7 D8 to D15 Key input interrupt KI0 to KI3
I/O A0 to A23 O
VCC2 VCC2
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 11 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
Table 1.8
Pin Definitions and Functions (2/4)
Function Bus control pins
Symbol A0/D0 to A7/D7
I/O
Power Supply VCC2
Description Output of address bits (A0 to A7) and input/output of data (D0 to D7) by time-division while accessing an external memory space with multiplexed bus Output of address bits (A8 to A15) and input/ output of data (D8 to D15) by time-division while accessing an external memory space with 16-bit multiplexed bus Output of byte control (BC0) and input/output of data (D0) by time-division while accessing an external memory space with multiplexed bus Chip select output Output of write, byte control, and read signals. Either WRx or WR and BCx can be selected by a program. Data is read when RD is low. * When WR0, WR1, and RD are selected, data is written to the following address: an even address, when WR0 is low an odd address, when WR1 is low on 16-bit external data bus * When WR, BC0, BC1, and RD are selected, data is written, when WR is low and the following address is accessed: an even address, when BC0 is low an odd address, when BC1 is low on 16-bit external data bus
I/O A8/D8 to A15/D15
I/O
VCC2
BC0/D0
I/O
CS0 to CS3 WR0/WR1/WR/ BC0/BC1/RD
VCC2 VCC2
O
O
VCC2
ALE
HOLD HLDA RDY
O I O I
VCC2 VCC2 VCC2 VCC2
Latch enable signal in multiplexed bus format The MCU is in a hold state while this pin is held low Low is output at this pin while the MCU is held in a hold state Bus cycle is extended by the CPU if low is input to this pin on the falling edge of the BCLK
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 12 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
Table 1.9
Pin Definitions and Functions (3/4)
Function I/O port
Symbol P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6, P8_7 P9_3 to P9_7 P10_0 to P10_7
I/O
Power Supply
Description I/O ports in CMOS. Each port can be programmed to input or output under the control of the direction register. Pull-up resistors are selected for following 4-pin units, but are enabled only for the input pins: Pi_0 to Pi_3 and Pi_4 to Pi_7 (i = 0 to 10). P7_0 and P7_1 outputs are N-channel open drain
I/O
VCC2
I/O
VCC1
Input port Timer A
P9_1 TA0OUT to TA4OUT TA0IN to TA4IN
I
VCC1 VCC1 VCC2 VCC1 VCC2 VCC1 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2
Input port in CMOS. Pull-up resistors are selected for P9_1 and P9_3 Timers A0 to A4 input/output. TA0OUT output assigned for port P7_0 is Nchannel open drain Timers A0 to A4 input Timers B0 to B5 input Three-phase motor control timer output
I/O
I I
Timer B Three-phase motor control timer output Serial interface
TB0IN to TB5IN U,U,V,V,W,W
O
CTS0 to CTS8 RTS0 to RTS8
I O I/O I O I/O I/O O I I
Handshake input Handshake output Transmit/receive clock input/output Serial data input Serial data output. TXD2 is N-channel open drain Serial data input/output. SDA2 output is N-channel open drain Transmit/receive clock input/output. SCL2 output is N-channel open drain Serial data output in slave mode. STXD2 is N-channel open drain Serial data input in slave mode Input to control serial interface special functions
CLK0 to CLK8 RXD0 to RXD8 TXD0 to TXD8 I2C bus (simplified) SDA0 to SDA6 SCL0 to SCL6 Serial interface special functions STXD0 to STXD6 SRXD0 to SRXD6
SS0 to SS6
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 13 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
1. Overview
Table 1.10
Pin Definitions and Functions (4/4)
Function A/D converter
Symbol AN_0 to AN_7 AN0_0 to AN0_7 AN2_0 to AN2_7
ADTRG
I/O I
Power Supply VCC1
Description Analog input for the A/D converter
I
VCC2
I I/O I O I I/O
VCC1 VCC1 VCC1 VCC1
-
External trigger input for the A/D converter Expanded analog input for the A/D converter and output in external op-amp connection mode Expanded analog input for the A/D converter Output for the D/A converter Reference voltage input for the A/D converter and D/A converter Input/output for the Intelligent I/O group 0. Either input capture or output compare is selectable Input/output for the Intelligent I/O group 1. Either input capture or output compare is selectable. IIO1_6 and IIO1_7 outputs assigned for ports P7_0 and P7_1 are N-channel open drain Input for the two-phase encoder Output for OC (output compare) of the Intelligent I/ O group 2. OUTC2_0 and OUTC2_2 assigned for ports P7_0 and P7_1 are N-channel open drain Clock input/output for the serial interface Receive data input for the serial interface Transmit data output for the serial interface. ISTXD2 assigned for port P7_0 is N-channel open drain Receive data input for the serial interface Transmit data output for the serial interface. IEOUT assigned for port P7_0 is N-channel open drain
ANEX0 ANEX1 D/A converter DA0, DA1 Reference voltage VREF input Intelligent I/O IIO0_0 to IIO0_7 IIO1_0 to IIO1_7
VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2
I/O
UD0A, UD0B, UD1A, UD1B OUTC2_0 to OUTC2_2
I
O
ISCLK2 ISRXD2 ISTXD2
I/O I O VCC1 VCC2
IEIN IEOUT
I O VCC1 VCC2
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 14 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
The CPU has 15 registers shown below. Of these, R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB make up a register bank, and there are two register banks. In addition to that, there are two groups of CPUinternal registers: fast interrupt registers and DMAC-associated registers.
General purpose registers R2R0 R3R1 R6R4 R7R5
b31
b23
b15
b7
b0
R2H R3H R6 R7
R2L R3L
R0H R1H R4 R5 A0 A1 A2 A3 SB FB USP ISP
R0L R1L Data registers (1)
Address registers (1)
Static base register (1) Frame base register (1) User stack pointer Interrupt stack pointer Interrupt vector table base register Program counter Flag register
INTB PC FLG
b31
b24 b23
b16 b15
b8 b7
b0
RND DP
IPL FU FO
U I OBSZDC
All blank fields are reserved.
Fast interrupt registers
b31
b0
SVF SVP VCT
Save flag register Save PC register Vector register
b0
DMAC-associated registers (2)
b31
b23
DMD0 DMD0 DMD0 DMD0 DCT0 DCT0 DCT0 DCT0 DCR0 DCR0 DCR0 DCR0 DSA0 DSA0 DSA0 DSA0 DSR0 DSR0 DSR0 DSR0 DDA0 DDA0 DDA0 DDA0 DDR0 DDR0 DDR0 DDR0
DMA mode register DMA terminal count register DMA terminal count reload register DMA source address register DMA source address reload register DMA destination address register DMA destination address reload register
Notes: 1. There are two banks of these registers. 2. There are four identical sets of DMAC-associated registers.
Figure 2.1
CPU Registers
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
2. Central Processing Unit (CPU)
2.1 2.1.1
General Purpose Registers Data Registers (R2R0, R3R1, R6R4, and R7R5)
These 32-bit registers are primarily used for transfers and arithmetic/logic operations. Each of the registers can be divided into the upper and the lower 16-bit registers, e.g. R2R0 can be divided into R2 and R0, R3R0 can be divided into R3 and R1, etc. Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: the upper (R2h, and R3H), the mid-upper (R2L, and R3L), the mid-lower (R0H, and R1H), and the lower (R0L, and R1L).
2.1.2
Address Registers (A0, A1, A2, and A3)
These 32-bit registers have the similar functions to the data registers. They are also used for address register indirect addressing and address register relative addressing.
2.1.3
Static Base Register (SB)
This 32-bit register is used for SB relative addressing.
2.1.4
Frame Base Register (FB)
This 32-bit register is used for FB relative addressing.
2.1.5
Program Counter (PC)
This 32-bit counter indicates the address of the instruction to be executed next.
2.1.6
Interrupt Vector Table Base Register (INTB)
This 32-bit register indicates the start address of a relocatable vector table.
2.1.7
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack pointer (ISP). They are switched by the U flag. Refer to 2.1.8 "Flag Register (FLG)" for details on the U flag. The stack pointer (USP/ISP) to be used can be switched by the stack pointer select flag (U flag). This flag is bit 7 in the flag register (FLG). A multiple of 4 should be set to USP or ISP, which enables faster interrupt sequence due to less memory access.
2.1.8
Flag Register (FLG)
This 32-bit register indicates the CPU status.
2.1.8.1
Carry Flag (C flag)
This flag has the carry, borrow, shifted-out bit, etc. generated in the arithmetic logic unit (ALU).
2.1.8.2
Debug Flag (D flag)
This flag is used exclusively for debugging. Only set this bit to 0.
2.1.8.3
Zero Flag (Z flag)
This flag becomes 1 when an operation results in 0; in all other cases, this flag becomes 0.
2.1.8.4
Sign Flag (S flag)
This flag becomes 1 when an operation results in a negative; in all other cases, this flag becomes 0. REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 16 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
2. Central Processing Unit (CPU)
2.1.8.5
Register Bank Select Flag (B flag)
This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the register bank 1 is selected.
2.1.8.6
Overflow Flag (O flag)
This flag becomes 1 if an operation results in an overflow; in all other cases, this flag becomes 0.
2.1.8.7
Interrupt Enable Flag (I flag)
This flag enables a maskable interrupt. It indicates 0 when an interrupt is disabled, and 1 when an interrupt is enabled. Once an interrupt is accepted, the flag is set to 0.
2.1.8.8
Stack Pointer Select Flag (U flag)
This flag indicates 0 when the interrupt stack pointer (ISP) is selected, and 1 when the user stack pointer (USP) is selected. It is set to 0 when a hardware interrupt is accepted or the INT instruction whose software interrupt number is 0 to 127 is executed.
2.1.8.9
Floating-point Underflow Flag (FU flag)
This flag becomes 1 if a floating point operation results in an underflow; in all other cases, this flag becomes 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.10
Floating-point Overflow Flag (FO flag)
This flag becomes 1 if a floating point operation results in an overflow; in all other cases, this flag becomes 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.11
Processor Interrupt Priority Level (IPL)
The 3-bit processor interrupt priority level (IPL) specifies eight processor interrupt priority levels from 0 to 7. If a requested interrupt's priority level is higher than the processor interrupt priority level (IPL), this interrupt is enabled. If the processor interrupt priority level (IPL) is set to 111b (level 7), any interrupt is disabled.
2.1.8.12
Fixed-point Designation Bit (DP bit)
This bit designates a fixed point. It also designates which part of the multiplication result should be taken. It is used for MULX instruction.
2.1.8.13
Floating-point Rounding Mode (RND)
The 2-bit floating point rounding mode designates a rounding mode for the operation result.
2.1.8.14
Reserved
The fields are written with 0. The read value is undefined.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 17 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
2. Central Processing Unit (CPU)
2.2
Fast Interrupt Registers
These registers are exclusively used to achieve high performance of interrupt sequence. Three types of register are shown as below.
2.2.1
Save Flag Register (SVF)
This 32-bit register is used to save the flag register when a fast interrupt is generated.
2.2.2
Save PC Register (SVP)
This 32-bit register is used to save the program counter when a fast interrupt is generated.
2.2.3
Vector Register (VCT)
This 32-bit register is used to indicate a jump address when a fast interrupt is generated.
2.3
DMAC-associated Registers
Seven types of register are shown as below.
2.3.1
DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)
These 32-bit registers are used to set DMA transfer mode, bit rate etc.
2.3.2
DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)
These 24-bit registers are used to set DMA transfer counting.
2.3.3
DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)
These 24-bit registers are used to set the reloaded value for DMA terminal count register.
2.3.4
DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)
These 32-bit registers are used to set DMA source address.
2.3.5
DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)
These 32-bit registers are used to set the reloaded value for DMA source address register.
2.3.6
DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)
These 32-bit registers are used to set DMA destination address.
2.3.7
DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and DDR3)
These 32-bit registers are used to set the reloaded value for DMA destination address register.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 18 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
3. Memory
3.
Memory
Figure 3.1 shows a memory mapping of the R32C/111 Group. The R32C/111 Group provides 4-Gbyte address space from 00000000h to FFFFFFFFh. The internal ROM is allocated from address FFFFFFFFh down. For example, a 512-Kbyte internal ROM is addressed from FFF80000h to FFFFFFFFh. The fixed interrupt vectors are allocated from address FFFFFFDCh to FFFFFFFFh in which the starting address of each interrupt handler is stored. The internal RAM is allocated from address 00000400h up. For example, a 40-Kbyte internal RAM is addressed from 00000400h to 0000A3FFh. Besides being used for data storage, the internal RAM functions as stack(s) for a subroutine and/or an interrupt handler. Special Function Registers (SFRs), consisting of control registers for peripheral functions, are allocated from address 00000000h to 000003FFh and from 00040000h to 0004FFFFh. Any blank spaces within the SFRs are reserved. No access is allowed. In memory expansion mode or microprocessor mode, some spaces are reserved. No access is allowed.
00000000h 00000400h
SFR1 Internal RAM
Internal RAM Capacity 40 Kbytes 63 Kbytes XXXXXXXXh 0000A400h 00010000h
XXXXXXXXh Reserved 00040000h 00050000h 00060000h
SFR2 Reserved Internal ROM (Data space) (1) Reserved
00062000h FFFFFFDCh Undefined instruction Overflow BRK instruction Reserved Reserved Watchdog timer (5) Reserved NMI Reset FFFFFFFFh
00080000h Internal ROM Capacity 256 Kbytes 384 Kbytes 512 Kbytes YYYYYYYYh FFFC0000h FFFA0000h FFF80000h YYYYYYYYh Internal ROM (4) FFFFFFFFh FFE00000h Reserved (3) External space (2)
Notes: 1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version. 2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h to FDFFFFFFh are inaccessible. 3. This space is reserved in memory expansion mode. It can be external space in microprocessor mode. 4. This space can be used in single-chip mode or memory expansion mode. It can be external space in microprocessor mode. 5. The watchdog timer interrupt shares the vector table with the oscillation stop detection interrupt and lowvoltage detection interrupt.
Figure 3.1
Memory Mapping
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 19 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List (1) to Table 4.24 SFR List (24) list the SFR details.
Table 4.1 SFR List (1)
Symbol Reset Value
Address Register 000000h 000001h 000002h 000003h 000004h Clock Control Register 000005h 000006h Flash Memory Control Register 000007h Protect Release Register 000008h 000009h 00000Ah 00000Bh 00000Ch 00000Dh 00000Eh 00000Fh 000010h External Bus Control Register 3 000011h 000012h Chip-select Boundary (between 2 and 3) Setting Register 000013h 000014h External Bus Control Register 2 000015h 000016h Chip-select Boundary (between 1 and 2) Setting Register 000017h 000018h External Bus Control Register 1 000019h 00001Ah Chip-select Boundary (between 0 and 1) Setting Register 00001Bh 00001Ch External Bus Control Register 0/Flash Memory Rewrite Bus 00001Dh Control Register 00001Eh Peripheral Bus Control Register 00001Fh 000020h to 00005Fh X: Undefined Blanks are reserved. No access is allowed.
CCR FMCR PRR
18h 01h 00h
EBC3 CB23 EBC2 CB12 EBC1 CB01 EBC0/FEBC PBC
0000h 00h 0000h 00h 0000h 00h 0000h 0504h
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Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.2
Address 000060h 000061h 000062h 000063h 000064h 000065h 000066h 000067h 000068h 000069h 00006Ah 00006Bh 00006Ch 00006Dh 00006Eh 00006Fh 000070h 000071h 000072h 000073h 000074h 000075h 000076h 000077h 000078h 000079h 00007Ah 00007Bh 00007Ch 00007Dh 00007Eh 00007Fh 000080h 000081h 000082h 000083h 000084h 000085h 000086h 000087h
SFR List (2)
Register Timer B5 Interrupt Control Register UART5 Transmit/NACK Interrupt Control Register UART2 Receive/ACK Interrupt Control Register UART6 Transmit/NACK Interrupt Control Register UART3 Receive/ACK Interrupt Control Register UART5/6 Bus Collision, Start/Stop Condition Detection Interrupt Control Register UART4 Receive/ACK Interrupt Control Register DMA0 Transfer Complete Interrupt Control Register UART0/3 Bus Collision, Start/Stop Condition Detection Interrupt Control Register DMA2 Transfer Complete Interrupt Control Register A/D Converter 0 Convert Completion Interrupt Control Register Timer A0 Interrupt Control Register Intelligent I/O Interrupt Control Register 0 Timer A2 Interrupt Control Register Intelligent I/O Interrupt Control Register 2 Timer A4 Interrupt Control Register Intelligent I/O Interrupt Control Register 4 UART0 Receive/ACK Interrupt Control Register Intelligent I/O Interrupt Control Register 6 UART1 Receive/ACK Interrupt Control Register Intelligent I/O Interrupt Control Register 8 Timer B1 Interrupt Control Register Intelligent I/O Interrupt Control Register 10 Timer B3 Interrupt Control Register INT5 Interrupt Control Register INT3 Interrupt Control Register INT1 Interrupt Control Register Symbol TB5IC S5TIC S2RIC S6TIC S3RIC BCN5IC/BCN6IC S4RIC DM0IC BCN0IC/BCN3IC DM2IC AD0IC TA0IC IIO0IC TA2IC IIO2IC TA4IC IIO4IC S0RIC IIO6IC S1RIC IIO8IC TB1IC IIO10IC TB3IC INT5IC INT3IC INT1IC Reset Value XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XX00 X000b
UART2 Transmit/NACK Interrupt Control Register UART5 Receive/ACK Interrupt Control Register UART3 Transmit/NACK Interrupt Control Register UART6 Receive/ACK Interrupt Control Register UART4 Transmit/NACK Interrupt Control Register
S2TIC S5RIC S3TIC S6RIC S4TIC BCN2IC
XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b
UART2 Bus Collision, Start/Stop Condition Detection Interrupt Control Register X: Undefined Blanks are reserved. No access is allowed.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 21 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.3
SFR List (3)
Symbol DM1IC BCN1IC/BCN4IC DM3IC KUPIC TA1IC IIO1IC TA3IC IIO3IC S0TIC IIO5IC S1TIC IIO7IC TB0IC IIO9IC TB2IC IIO11IC TB4IC INT4IC INT2IC INT0IC IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Reset Value XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XX00 X000b 0000 0XX1b 0000 0XX1b 0000 0X01b 0000 XXX1b 000X 0XX1b 000X 0XX1b 000X 0XX1b X00X 0XX1b XX0X 0XX1b 0000 0XX1b 0000 0XX1b 0000 0XX1b
Address Register 000088h DMA1 Transfer Complete Interrupt Control Register 000089h UART1/4 Bus Collision, Start/Stop Condition Detection Interrupt Control Register 00008Ah DMA3 Transfer Complete Interrupt Control Register 00008Bh Key Input Interrupt Control Register 00008Ch Timer A1 Interrupt Control Register 00008Dh Intelligent I/O Interrupt Control Register 1 00008Eh Timer A3 Interrupt Control Register 00008Fh Intelligent I/O Interrupt Control Register 3 000090h UART0 Transmit/NACK Interrupt Control Register 000091h Intelligent I/O Interrupt Control Register 5 000092h UART1 Transmit/NACK Interrupt Control Register 000093h Intelligent I/O Interrupt Control Register 7 000094h Timer B0 Interrupt Control Register 000095h Intelligent I/O Interrupt Control Register 9 000096h Timer B2 Interrupt Control Register 000097h Intelligent I/O Interrupt Control Register 11 000098h Timer B4 Interrupt Control Register 000099h 00009Ah INT4 Interrupt Control Register 00009Bh 00009Ch INT2 Interrupt Control Register 00009Dh 00009Eh INT0 Interrupt Control Register 00009Fh 0000A0h Intelligent I/O Interrupt Request Register 0 0000A1h Intelligent I/O Interrupt Request Register 1 0000A2h Intelligent I/O Interrupt Request Register 2 0000A3h Intelligent I/O Interrupt Request Register 3 0000A4h Intelligent I/O Interrupt Request Register 4 0000A5h Intelligent I/O Interrupt Request Register 5 0000A6h Intelligent I/O Interrupt Request Register 6 0000A7h Intelligent I/O Interrupt Request Register 7 0000A8h Intelligent I/O Interrupt Request Register 8 0000A9h Intelligent I/O Interrupt Request Register 9 0000AAh Intelligent I/O Interrupt Request Register 10 0000ABh Intelligent I/O Interrupt Request Register 11 0000ACh 0000ADh 0000AEh 0000AFh X: Undefined Blanks are reserved. No access is allowed.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 22 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.4
SFR List (4)
Symbol IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Address Register 0000B0h Intelligent I/O Interrupt Enable Register 0 0000B1h Intelligent I/O Interrupt Enable Register 1 0000B2h Intelligent I/O Interrupt Enable Register 2 0000B3h Intelligent I/O Interrupt Enable Register 3 0000B4h Intelligent I/O Interrupt Enable Register 4 0000B5h Intelligent I/O Interrupt Enable Register 5 0000B6h Intelligent I/O Interrupt Enable Register 6 0000B7h Intelligent I/O Interrupt Enable Register 7 0000B8h Intelligent I/O Interrupt Enable Register 8 0000B9h Intelligent I/O Interrupt Enable Register 9 0000BAh Intelligent I/O Interrupt Enable Register 10 0000BBh Intelligent I/O Interrupt Enable Register 11 0000BCh 0000BDh 0000BEh 0000BFh 0000C0h 0000C1h 0000C2h 0000C3h 0000C4h 0000C5h 0000C6h 0000C7h 0000C8h 0000C9h 0000CAh 0000CBh 0000CCh 0000CDh 0000CEh 0000CFh 0000D0h 0000D1h 0000D2h 0000D3h 0000D4h 0000D5h 0000D6h 0000D7h 0000D8h 0000D9h 0000DAh 0000DBh 0000DCh 0000DDh UART7 Transmit Interrupt Control Register 0000DEh 0000DFh UART8 Transmit Interrupt Control Register X: Undefined Blanks are reserved. No access is allowed.
S7TIC S8TIC
XXXX X000b XXXX X000b
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 23 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.5
SFR List (5)
Symbol Reset Value
Address Register 0000E0h 0000E1h 0000E2h 0000E3h 0000E4h 0000E5h 0000E6h 0000E7h 0000E8h 0000E9h 0000EAh 0000EBh 0000ECh 0000EDh 0000EEh 0000EFh 0000F0h 0000F1h 0000F2h 0000F3h 0000F4h 0000F5h 0000F6h 0000F7h 0000F8h 0000F9h 0000FAh 0000FBh 0000FCh 0000FDh UART7 Receive Interrupt Control Register 0000FEh 0000FFh UART8 Receive Interrupt Control Register 000100h Group 1 Time Measurement/Waveform Generation Register 0 000101h 000102h Group 1 Time Measurement/Waveform Generation Register 1 000103h 000104h Group 1 Time Measurement/Waveform Generation Register 2 000105h 000106h Group 1 Time Measurement/Waveform Generation Register 3 000107h X: Undefined Blanks are reserved. No access is allowed.
S7RIC S8RIC G1TM0/G1PO0 G1TM1/G1PO1 G1TM2/G1PO2 G1TM3/G1PO3
XXXX X000b XXXX X000b XXXXh XXXXh XXXXh XXXXh
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 24 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.6
SFR List (6)
Symbol G1TM4/G1PO4 G1TM5/G1PO5 G1TM6/G1PO6 G1TM7/G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS Reset Value XXXXh XXXXh XXXXh XXXXh 0000 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 00h 00h 00h 00h 00h 00h 00h 00h XXXXh 00h 0000 0000b 00h 00h 00h 00h
Address Register 000108h Group 1 Time Measurement/Waveform Generation Register 4 000109h 00010Ah Group 1 Time Measurement/Waveform Generation Register 5 00010Bh 00010Ch Group 1 Time Measurement/Waveform Generation Register 6 00010Dh 00010Eh Group 1 Time Measurement/Waveform Generation Register 7 00010Fh 000110h Group 1 Waveform Generation Control Register 0 000111h Group 1 Waveform Generation Control Register 1 000112h Group 1 Waveform Generation Control Register 2 000113h Group 1 Waveform Generation Control Register 3 000114h Group 1 Waveform Generation Control Register 4 000115h Group 1 Waveform Generation Control Register 5 000116h Group 1 Waveform Generation Control Register 6 000117h Group 1 Waveform Generation Control Register 7 000118h Group 1 Time Measurement Control Register 0 000119h Group 1 Time Measurement Control Register 1 00011Ah Group 1 Time Measurement Control Register 2 00011Bh Group 1 Time Measurement Control Register 3 00011Ch Group 1 Time Measurement Control Register 4 00011Dh Group 1 Time Measurement Control Register 5 00011Eh Group 1 Time Measurement Control Register 6 00011Fh Group 1 Time Measurement Control Register 7 000120h Group 1 Base Timer Register 000121h 000122h Group 1 Base Timer Control Register 0 000123h Group 1 Base Timer Control Register 1 000124h Group 1 Timer Measurement Prescaler Register 6 000125h Group 1 Timer Measurement Prescaler Register 7 000126h Group 1 Function Enable Register 000127h Group 1 Function Select Register 000128h 000129h 00012Ah 00012Bh 00012Ch 00012Dh 00012Eh 00012Fh 000130h to 00013Fh X: Undefined Blanks are reserved. No access is allowed.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 25 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.7
SFR List (7)
Symbol G2PO0 G2PO1 G2PO2 G2PO3 G2PO4 G2PO5 G2PO6 G2PO7 G2POCR0 G2POCR1 G2POCR2 G2POCR3 G2POCR4 G2POCR5 G2POCR6 G2POCR7 Reset Value XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b
Address Register 000140h Group 2 Waveform Generation Register 0 000141h 000142h Group 2 Waveform Generation Register 1 000143h 000144h Group 2 Waveform Generation Register 2 000145h 000146h Group 2 Waveform Generation Register 3 000147h 000148h Group 2 Waveform Generation Register 4 000149h 00014Ah Group 2 Waveform Generation Register 5 00014Bh 00014Ch Group 2 Waveform Generation Register 6 00014Dh 00014Eh Group 2 Waveform Generation Register 7 00014Fh 000150h Group 2 Waveform Generation Control Register 0 000151h Group 2 Waveform Generation Control Register 1 000152h Group 2 Waveform Generation Control Register 2 000153h Group 2 Waveform Generation Control Register 3 000154h Group 2 Waveform Generation Control Register 4 000155h Group 2 Waveform Generation Control Register 5 000156h Group 2 Waveform Generation Control Register 6 000157h Group 2 Waveform Generation Control Register 7 000158h 000159h 00015Ah 00015Bh 00015Ch 00015Dh 00015Eh 00015Fh 000160h Group 2 Base Timer Register 000161h 000162h Group 2 Base Timer Control Register 0 000163h Group 2 Base Timer Control Register 1 000164h Base Timer Start Register 000165h 000166h Group 2 Function Enable Register 000167h Group 2 RTP Output Buffer Register 000168h 000169h 00016Ah Group 2 Serial Interface Mode Register 00016Bh Group 2 Serial Interface Control Register 00016Ch Group 2 SI/O Transmit Buffer Register 00016Dh 00016Eh Group 2 SI/O Receive Buffer Register 00016Fh X: Undefined Blanks are reserved. No access is allowed.
G2BT G2BCR0 G2BCR1 BTSR G2FE G2RTP
XXXXh 00h 0000 0000b XXXX 0000b 00h 00h
G2MR G2CR G2TB G2RB
00XX X000b 0000 X110b XXXXh XXXXh
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 26 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.8
SFR List (8)
Symbol IEAR IECR IETIF IERIF Reset Value XXXXh 00XX X000b XXX0 0000b XXX0 0000b
Address Register 000170h Group 2 IE Bus Address Register 000171h 000172h Group 2 IE Bus Control Register 000173h Group 2 IE Bus Transmit Interrupt Source Detect Register 000174h Group 2 IE Bus Receive Interrupt Source Detect Register 000175h 000176h 000177h 000178h 000179h 00017Ah 00017Bh 00017Ch 00017Dh 00017Eh 00017Fh 000180h Group 0 Time Measurement/Waveform Generation Register 0 000181h 000182h Group 0 Time Measurement/Waveform Generation Register 1 000183h 000184h Group 0 Time Measurement/Waveform Generation Register 2 000185h 000186h Group 0 Time Measurement/Waveform Generation Register 3 000187h 000188h Group 0 Time Measurement/Waveform Generation Register 4 000189h 00018Ah Group 0 Time Measurement/Waveform Generation Register 5 00018Bh 00018Ch Group 0 Time Measurement/Waveform Generation Register 6 00018Dh 00018Eh Group 0 Time Measurement/Waveform Generation Register 7 00018Fh 000190h Group 0 Waveform Generation Control Register 0 000191h Group 0 Waveform Generation Control Register 1 000192h Group 0 Waveform Generation Control Register 2 000193h Group 0 Waveform Generation Control Register 3 000194h Group 0 Waveform Generation Control Register 4 000195h Group 0 Waveform Generation Control Register 5 000196h Group 0 Waveform Generation Control Register 6 000197h Group 0 Waveform Generation Control Register 7 000198h Group 0 Time Measurement Control Register 0 000199h Group 0 Time Measurement Control Register 1 00019Ah Group 0 Time Measurement Control Register 2 00019Bh Group 0 Time Measurement Control Register 3 00019Ch Group 0 Time Measurement Control Register 4 00019Dh Group 0 Time Measurement Control Register 5 00019Eh Group 0 Time Measurement Control Register 6 00019Fh Group 0 Time Measurement Control Register 7 X: Undefined Blanks are reserved. No access is allowed.
G0TM0/G0PO0 G0TM1/G0PO1 G0TM2/G0PO2 G0TM3/G0PO3 G0TM4/G0PO4 G0TM5/G0PO5 G0TM6/G0PO6 G0TM7/G0PO7 G0POCR0 G0POCR1 G0POCR2 G0POCR3 G0POCR4 G0POCR5 G0POCR6 G0POCR7 G0TMCR0 G0TMCR1 G0TMCR2 G0TMCR3 G0TMCR4 G0TMCR5 G0TMCR6 G0TMCR7
XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0000 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 00h 00h 00h 00h 00h 00h 00h 00h
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 27 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.9
SFR List (9)
Symbol G0BT G0BCR0 G0BCR1 G0TPR6 G0TPR7 G0FE G0FS Reset Value XXXXh 00h 0000 0000b 00h 00h 00h 00h
Address Register 0001A0h Group 0 Base Timer Register 0001A1h 0001A2h Group 0 Base Timer Control Register 0 0001A3h Group 0 Base Timer Control Register 1 0001A4h Group 0 Timer Measurement Prescaler Register 6 0001A5h Group 0 Timer Measurement Prescaler Register 7 0001A6h Group 0 Function Enable Register 0001A7h Group 0 Function Select Register 0001A8h 0001A9h 0001AAh 0001ABh 0001ACh 0001ADh 0001AEh 0001AFh 0001B0h 0001B1h 0001B2h 0001B3h 0001B4h 0001B5h 0001B6h 0001B7h 0001B8h 0001B9h 0001BAh 0001BBh 0001BCh 0001BDh 0001BEh 0001BFh 0001C0h 0001C1h 0001C2h 0001C3h 0001C4h UART5 Special Mode Register 4 0001C5h UART5 Special Mode Register 3 0001C6h UART5 Special Mode Register 2 0001C7h UART5 Special Mode Register 0001C8h UART5 Transmit/Receive Mode Register 0001C9h UART5 Bit Rate Register 0001CAh UART5 Transmit Buffer Register 0001CBh 0001CCh UART5 Transmit/Receive Control Register 0 0001CDh UART5 Transmit/Receive Control Register 1 0001CEh UART5 Receive Buffer Register 0001CFh X: Undefined Blanks are reserved. No access is allowed.
U5SMR4 U5SMR3 U5SMR2 U5SMR U5MR U5BRG U5TB U5C0 U5C1 U5RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 28 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.10
SFR List (10)
Symbol Reset Value
Address Register 0001D0h 0001D1h 0001D2h 0001D3h 0001D4h UART6 Special Mode Register 4 0001D5h UART6 Special Mode Register 3 0001D6h UART6 Special Mode Register 2 0001D7h UART6 Special Mode Register 0001D8h UART6 Transmit/Receive Mode Register 0001D9h UART6 Bit Rate Register 0001DAh UART6 Transmit Buffer Register 0001DBh 0001DCh UART6 Transmit/Receive Control Register 0 0001DDh UART6 Transmit/Receive Control Register 1 0001DEh UART6 Receive Buffer Register 0001DFh 0001E0h UART7 Transmit/Receive Mode Register 0001E1h UART7 Bit Rate Register 0001E2h UART7 Transmit Buffer Register 0001E3h 0001E4h UART7 Transmit/Receive Control Register 0 0001E5h UART7 Transmit/Receive Control Register 1 0001E6h UART7 Receive Buffer Register 0001E7h 0001E8h UART8 Transmit/Receive Mode Register 0001E9h UART8 Bit Rate Register 0001EAh UART8 Transmit Buffer Register 0001EBh 0001ECh UART8 Transmit/Receive Control Register 0 0001EDh UART8 Transmit/Receive Control Register 1 0001EEh UART8 Receive Buffer Register 0001EFh 0001F0h UART7, UART8 Transmit/Receive Control Register 2 0001F1h 0001F2h 0001F3h 0001F4h 0001F5h 0001F6h 0001F7h 0001F8h 0001F9h 0001FAh 0001FBh 0001FCh 0001FDh 0001FEh 0001FFh X: Undefined Blanks are reserved. No access is allowed.
U6SMR4 U6SMR3 U6SMR2 U6SMR U6MR U6BRG U6TB U6C0 U6C1 U6RB U7MR U7BRG U7TB U7C0 U7C1 U7RB U8MR U8BRG U8TB U8C0 U8C1 U8RB U78CON
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 00h XXh XXXXh 00X0 1000b XXXX 0010b XXXX XXXXb XXXX 000Xb 00h XXh XXXXh 00X0 1000b XXXX 0010b XXXX XXXXb XXXX 000Xb X000 0000b
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 29 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.11
SFR List (11)
Symbol Reset Value
Address Register 000200h to 0002BFh 0002C0h X0 Register Y0 Register 0002C1h 0002C2h X1 Register Y1 Register 0002C3h 0002C4h X2 Register Y2 Register 0002C5h 0002C6h X3 Register Y3 Register 0002C7h 0002C8h X4 Register Y4 Register 0002C9h 0002CAh X5 Register Y5 Register 0002CBh 0002CCh X6 Register Y6 Register 0002CDh 0002CEh X7 Register Y7 Register 0002CFh 0002D0h X8 Register Y8 Register 0002D1h 0002D2h X9 Register Y9 Register 0002D3h 0002D4h X10 Register Y10 Register 0002D5h 0002D6h X11 Register Y11 Register 0002D7h 0002D8h X12 Register Y12 Register 0002D9h 0002DAh X13 Register Y13 Register 0002DBh 0002DCh X14 Register Y14 Register 0002DDh 0002DEh X15 Register Y15 Register 0002DFh 0002E0h XY Control Register 0002E1h 0002E2h 0002E3h 0002E4h UART1 Special Mode Register 4 0002E5h UART1 Special Mode Register 3 0002E6h UART1 Special Mode Register 2 0002E7h UART1 Special Mode Register 0002E8h UART1 Transmit/Receive Mode Register 0002E9h UART1 Bit Rate Register 0002EAh UART1 Transmit Buffer Register 0002EBh 0002ECh UART1 Transmit/Receive Control Register 0 0002EDh UART1 Transmit/Receive Control Register 1 0002EEh UART1 Receive Buffer Register 0002EFh X: Undefined Blanks are reserved. No access is allowed.
X0R, Y0R X1R, Y1R X2R, Y2R X3R, Y3R X4R, Y4R X5R, Y5R X6R, Y6R X7R, Y7R X8R, Y8R X9R, Y9R X10R, Y10R X11R, Y11R X12R, Y12R X13R, Y13R X14R, Y14R X15R, Y15R XYC
XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXX XX00b
U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 30 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.12
SFR List (12)
Symbol Reset Value
Address Register 0002F0h 0002F1h 0002F2h 0002F3h 0002F4h UART4 Special Mode Register 4 0002F5h UART4 Special Mode Register 3 0002F6h UART4 Special Mode Register 2 0002F7h UART4 Special Mode Register 0002F8h UART4 Transmit/Receive Mode Register 0002F9h UART4 Bit Rate Register 0002FAh UART4 Transmit Buffer Register 0002FBh 0002FCh UART4 Transmit/Receive Control Register 0 0002FDh UART4 Transmit/Receive Control Register 1 0002FEh UART4 Receive Buffer Register 0002FFh 000300h Count Start Register for Timers B3, B4 and B5 000301h 000302h Timer A1-1 Register 000303h 000304h Timer A2-1 Register 000305h 000306h Timer A4-1 Register 000307h 000308h Three-phase PWM Control Register 0 000309h Three-phase PWM Control Register 1 00030Ah Three-phase Output Buffer Register 0 00030Bh Three-phase Output Buffer Register 1 00030Ch Dead Time Timer 00030Dh Timer B2 Interrupt Generating Frequency Set Counter 00030Eh 00030Fh 000310h Timer B3 Register 000311h 000312h Timer B4 Register 000313h 000314h Timer B5 Register 000315h 000316h 000317h 000318h 000319h 00031Ah 00031Bh Timer B3 Mode Register 00031Ch Timer B4 Mode Register 00031Dh Timer B5 Mode Register 00031Eh 00031Fh X: Undefined Blanks are reserved. No access is allowed.
U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 000X XXXXb XXXXh XXXXh XXXXh 00h 00h XX11 1111b XX11 1111b XXh XXh
TB3 TB4 TB5
XXXXh XXXXh XXXXh
TB3MR TB4MR TB5MR
00XX 0000b 00XX 0000b 00XX 0000b
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 31 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.13
SFR List (13)
Symbol Reset Value
Address Register 000320h 000321h 000322h 000323h 000324h UART3 Special Mode Register 4 000325h UART3 Special Mode Register 3 000326h UART3 Special Mode Register 2 000327h UART3 Special Mode Register 000328h UART3 Transmit/Receive Mode Register 000329h UART3 Bit Rate Register 00032Ah UART3 Transmit Buffer Register 00032Bh 00032Ch UART3 Transmit/Receive Control Register 0 00032Dh UART3 Transmit/Receive Control Register 1 00032Eh UART3 Receive Buffer Register 00032Fh 000330h 000331h 000332h 000333h 000334h UART2 Special Mode Register 4 000335h UART2 Special Mode Register 3 000336h UART2 Special Mode Register 2 000337h UART2 Special Mode Register 000338h UART2 Transmission/Receive Mode Register 000339h UART2 Bit Rate Register 00033Ah UART2 Transmit Buffer Register 00033Bh 00033Ch UART2 Transmit/Receive Control Register 0 00033Dh UART2 Transmit/Receive Control Register 1 00033Eh UART2 Receive Buffer Register 00033Fh 000340h Count Start Register 000341h Clock Prescaler Reset Register 000342h One-shot Start Register 000343h Trigger Select Register 000344h Increment/Decrement Counting Select Register 000345h 000346h Timer A0 Register 000347h 000348h Timer A1 Register 000349h 00034Ah Timer A2 Register 00034Bh 00034Ch Timer A3 Register 00034Dh 00034Eh Timer A4 Register 00034Fh X: Undefined Blanks are reserved. No access is allowed.
U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 00h 0XXX XXXXb 00h 00h 0000 0000b XXXXh XXXXh XXXXh XXXXh XXXXh
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 32 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.14
SFR List (14)
Symbol TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR Reset Value XXXXh XXXXh XXXXh 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 00XX 0000b 00XX 0000b 00XX 0000b XXXX XXX0b 0000 0000b
Address Register 000350h Timer B0 Register 000351h 000352h Timer B1 Register 000353h 000354h Timer B2 Register 000355h 000356h Timer A0 Mode Register 000357h Timer A1 Mode Register 000358h Timer A2 Mode Register 000359h Timer A3 Mode Register 00035Ah Timer A4 Mode Register 00035Bh Timer B0 Mode Register 00035Ch Timer B1 Mode Register 00035Dh Timer B2 Mode Register 00035Eh Timer B2 Special Mode Register 00035Fh Count Source Prescaler Register 000360h 000361h 000362h 000363h 000364h UART0 Special Mode Register 4 000365h UART0 Special Mode Register 3 000366h UART0 Special Mode Register 2 000367h UART0 Special Mode Register 000368h UART0 Transmit/Receive Mode Register 000369h UART0 Bit Rate Register 00036Ah UART0 Transmit Buffer Register 00036Bh 00036Ch UART0 Transmit/Receive Control Register 0 00036Dh UART0 Transmit/Receive Control Register 1 00036Eh UART0 Receive Buffer Register 00036Fh 000370h 000371h 000372h 000373h 000374h 000375h 000376h 000377h 000378h 000379h 00037Ah 00037Bh 00037Ch CRC Data Register 00037Dh 00037Eh CRC Input Register 00037Fh X: Undefined Blanks are reserved. No access is allowed.
U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
CRCD CRCIN
XXXXh XXh
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 33 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.15
SFR List (15)
Symbol AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 Reset Value 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh
Address Register 000380h A/D0 Register 0 000381h 000382h A/D0 Register 1 000383h 000384h A/D0 Register 2 000385h 000386h A/D0 Register 3 000387h 000388h A/D0 Register 4 000389h 00038Ah A/D0 Register 5 00038Bh 00038Ch A/D0 Register 6 00038Dh 00038Eh A/D0 Register 7 00038Fh 000390h 000391h 000392h A/D0 Control Register 4 000393h 000394h A/D0 Control Register 2 000395h A/D0 Control Register 3 000396h A/D0 Control Register 0 000397h A/D0 Control Register 1 000398h D/A Register 0 000399h 00039Ah D/A Register 1 00039Bh 00039Ch D/A Control Register 00039Dh 00039Eh 00039Fh 0003A0h 0003A1h 0003A2h 0003A3h 0003A4h 0003A5h 0003A6h 0003A7h 0003A8h 0003A9h 0003AAh 0003ABh 0003ACh 0003ADh 0003AEh 0003AFh X: Undefined Blanks are reserved. No access is allowed.
AD0CON4 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON
XXXX 00XXb X00X X000b XXXX X000b 00h 00h XXh XXh XXXX XX00b
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 34 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.16
SFR List (16)
Symbol Reset Value
Address Register 0003B0h 0003B1h 0003B2h 0003B3h 0003B4h 0003B5h 0003B6h 0003B7h 0003B8h 0003B9h 0003BAh 0003BBh 0003BCh 0003BDh 0003BEh 0003BFh 0003C0h Port P0 Register 0003C1h Port P1 Register 0003C2h Port P0 Direction Register 0003C3h Port P1 Direction Register 0003C4h Port P2 Register 0003C5h Port P3 Register 0003C6h Port P2 Direction Register 0003C7h Port P3 Direction Register 0003C8h Port P4 Register 0003C9h Port P5 Register 0003CAh Port P4 Direction Register 0003CBh Port P5 Direction Register 0003CCh Port P6 Register 0003CDh Port P7 Register 0003CEh Port P6 Direction Register 0003CFh Port P7 Direction Register 0003D0h Port P8 Register 0003D1h Port P9 Register 0003D2h Port P8 Direction Register 0003D3h Port P9 Direction Register 0003D4h Port P10 Register 0003D5h 0003D6h Port P10 Direction Register 0003D7h 0003D8h 0003D9h 0003DAh 0003DBh 0003DCh 0003DDh 0003DEh 0003DFh X: Undefined Blanks are reserved. No access is allowed.
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10
XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00X0 0000b 00h XXh 00h
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 35 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.17
SFR List (17)
Symbol Reset Value
Address Register 0003E0h 0003E1h 0003E2h 0003E3h 0003E4h 0003E5h 0003E6h 0003E7h 0003E8h 0003E9h 0003EAh 0003EBh 0003ECh 0003EDh 0003EEh 0003EFh 0003F0h Pull-up Control Register 0 0003F1h Pull-up Control Register 1 0003F2h Pull-up Control Register 2 0003F3h Pull-up Control Register 3 0003F4h 0003F5h 0003F6h 0003F7h 0003F8h 0003F9h 0003FAh 0003FBh 0003FCh 0003FDh 0003FEh 0003FFh Port Control Register X: Undefined Blanks are reserved. No access is allowed.
PUR0 PUR1 PUR2 PUR3
0000 0000b XXXX 0000b 0000 0000b XXXX XX00b
PCR
XXXX XXX0b
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 36 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.18
SFR List (18)
Symbol FMR0 FMSR0 Reset Value 0X01 XX00b 1000 0000b
Address Register 040000h Flash Memory Control Register 0 040001h Flash Memory Status Register 0 040002h 040003h 040004h 040005h 040006h 040007h 040008h Flash Register Protection Unlock Register 0 040009h Flash Memory Control Register 1 04000Ah Block Protect Bit Monitor Register 0 04000Bh Block Protect Bit Monitor Register 1 04000Ch 04000Dh 04000Eh 04000Fh 040010h 040011h 040012h 040013h 040014h 040015h 040016h 040017h 040018h 040019h 04001Ah 04001Bh 04001Ch 04001Dh 04001Eh 04001Fh 040020h PLL Control Register 0 040021h PLL Control Register 1 040022h 040023h 040024h 040025h 040026h 040027h 040028h 040029h 04002Ah 04002Bh 04002Ch 04002Dh 04002Eh 04002Fh X: Undefined Blanks are reserved. No access is allowed. Note: 1. The status of protect bit of each block in flash memory is reflected.
FPR0 FMR1 FBPM0 FBPM1
00h 0000 0010b ??X? ????b (1) XXX? ????b (1)
PLC0 PLC1
0000 0001b 0001 1111b
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 37 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.19
SFR List (19)
Symbol Reset Value
Address Register 040030h to 04003Fh 040040h 040041h 040042h 040043h 040044h Processor Mode Register 0 (1)
PM0
1000 0000b (CNVSS pin = Low) 0000 0011b (CNVSS pin = High) 0000 1000b 0010 0000b 00h XXXX X000b 0000 0000b 00h
040045h 040046h System Clock Control Register 0 040047h System Clock Control Register 1 040048h Processor Mode Register 3 040049h 04004Ah Protect Register 04004Bh 04004Ch Protect Register 3 04004Dh Oscillator Stop Detection Register 04004Eh 04004Fh 040050h 040051h 040052h 040053h Processor Mode Register 2 040054h Chip Select Output Pin Setting Register 0 040055h Chip Select Output Pin Setting Register 1 040056h 040057h 040058h 040059h 04005Ah Low Speed Mode Clock Control Register 04005Bh 04005Ch 04005Dh 04005Eh 04005Fh 040060h Voltage Regulator Control Register 040061h 040062h Low Voltage Detector Control Register 040063h 040064h Detection Voltage Configuration Register 040065h 040066h 040067h 040068h to 04008Fh X: Undefined Blanks are reserved. No access is allowed.
CM0 CM1 PM3 PRCR PRCR3 CM2
PM2 CSOP0 CSOP1
00h 1000 XXXXb 01X0 XXXXb
CM3
XXXX XX00b
VRCR LVDC DVCR
0000 0000b 0000 XX00b 0000 XXXXb
Note: 1. The value in the PM0 register remains unchanged even after a watchdog timer reset operation.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 38 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.20
SFR List (20)
Symbol Reset Value
Address Register 040090h 040091h 040092h 040093h 040094h 040095h 040096h 040097h Three-phase Output Buffer Control Register 040098h Input Function Select Register 0 040099h 04009Ah Input Function Select Register 2 04009Bh Input Function Select Register 3 04009Ch 04009Dh 04009Eh 04009Fh 0400A0h Port P0_0 Port Function Select Register 0400A1h Port P1_0 Port Function Select Register 0400A2h Port P0_1 Port Function Select Register 0400A3h Port P1_1 Port Function Select Register 0400A4h Port P0_2 Port Function Select Register 0400A5h Port P1_2 Port Function Select Register 0400A6h Port P0_3 Port Function Select Register 0400A7h Port P1_3 Port Function Select Register 0400A8h Port P0_4 Port Function Select Register 0400A9h Port P1_4 Port Function Select Register 0400AAh Port P0_5 Port Function Select Register 0400ABh Port P1_5 Port Function Select Register 0400ACh Port P0_6 Port Function Select Register 0400ADh Port P1_6 Port Function Select Register 0400AEh Port P0_7 Port Function Select Register 0400AFh Port P1_7 Port Function Select Register 0400B0h Port P2_0 Port Function Select Register 0400B1h Port P3_0 Port Function Select Register 0400B2h Port P2_1 Port Function Select Register 0400B3h Port P3_1 Port Function Select Register 0400B4h Port P2_2 Port Function Select Register 0400B5h Port P3_2 Port Function Select Register 0400B6h Port P2_3 Port Function Select Register 0400B7h Port P3_3 Port Function Select Register 0400B8h Port P2_4 Port Function Select Register 0400B9h Port P3_4 Port Function Select Register 0400BAh Port P2_5 Port Function Select Register 0400BBh Port P3_5 Port Function Select Register 0400BCh Port P2_6 Port Function Select Register 0400BDh Port P3_6 Port Function Select Register 0400BEh Port P2_7 Port Function Select Register 0400BFh Port P3_7 Port Function Select Register X: Undefined Blanks are reserved. No access is allowed.
IOBC IFS0 IFS2 IFS3
0XXX XXXXb XXXX XXX0b 000X 00XXb XXXX XX00b
P0_0S P1_0S P0_1S P1_1S P0_2S P1_2S P0_3S P1_3S P0_4S P1_4S P0_5S P1_5S P0_6S P1_6S P0_7S P1_7S P2_0S P3_0S P2_1S P3_1S P2_2S P3_2S P2_3S P3_3S P2_4S P3_4S P2_5S P3_5S P2_6S P3_6S P2_7S P3_7S
0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 39 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.21
SFR List (21)
Symbol P4_0S P5_0S P4_1S P5_1S P4_2S P5_2S P4_3S P5_3S P4_4S P5_4S P4_5S P5_5S P4_6S P5_6S P4_7S P5_7S P6_0S P7_0S P6_1S P7_1S P6_2S P7_2S P6_3S P7_3S P6_4S P7_4S P6_5S P7_5S P6_6S P7_6S P6_7S P7_7S P8_0S P8_1S P8_2S P8_3S P9_3S P8_4S P9_4S P9_5S P8_6S P9_6S P8_7S P9_7S Reset Value XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b XXXX X000b
Address Register 0400C0h Port P4_0 Port Function Select Register 0400C1h Port P5_0 Port Function Select Register 0400C2h Port P4_1 Port Function Select Register 0400C3h Port P5_1 Port Function Select Register 0400C4h Port P4_2 Port Function Select Register 0400C5h Port P5_2 Port Function Select Register 0400C6h Port P4_3 Port Function Select Register 0400C7h Port P5_3 Port Function Select Register 0400C8h Port P4_4 Port Function Select Register 0400C9h Port P5_4 Port Function Select Register 0400CAh Port P4_5 Port Function Select Register 0400CBh Port P5_5 Port Function Select Register 0400CCh Port P4_6 Port Function Select Register 0400CDh Port P5_6 Port Function Select Register 0400CEh Port P4_7 Port Function Select Register 0400CFh Port P5_7 Port Function Select Register 0400D0h Port P6_0 Port Function Select Register 0400D1h Port P7_0 Port Function Select Register 0400D2h Port P6_1 Port Function Select Register 0400D3h Port P7_1 Port Function Select Register 0400D4h Port P6_2 Port Function Select Register 0400D5h Port P7_2 Port Function Select Register 0400D6h Port P6_3 Port Function Select Register 0400D7h Port P7_3 Port Function Select Register 0400D8h Port P6_4 Port Function Select Register 0400D9h Port P7_4 Port Function Select Register 0400DAh Port P6_5 Port Function Select Register 0400DBh Port P7_5 Port Function Select Register 0400DCh Port P6_6 Port Function Select Register 0400DDh Port P7_6 Port Function Select Register 0400DEh Port P6_7 Port Function Select Register 0400DFh Port P7_7 Port Function Select Register 0400E0h Port P8_0 Port Function Select Register 0400E1h 0400E2h Port P8_1 Port Function Select Register 0400E3h 0400E4h Port P8_2 Port Function Select Register 0400E5h 0400E6h Port P8_3 Port Function Select Register 0400E7h Port P9_3 Port Function Select Register 0400E8h Port P8_4 Port Function Select Register 0400E9h Port P9_4 Port Function Select Register 0400EAh 0400EBh Port P9_5 Port Function Select Register 0400ECh Port P8_6 Port Function Select Register 0400EDh Port P9_6 Port Function Select Register 0400EEh Port P8_7 Port Function Select Register 0400EFh Port P9_7 Port Function Select Register X: Undefined Blanks are reserved. No access is allowed.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 40 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.22
SFR List (22)
Symbol P10_0S P10_1S P10_2S P10_3S P10_4S P10_5S P10_6S P10_7S Reset Value 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b 0XXX X000b
Address Register 0400F0h Port P10_0 Port Function Select Register 0400F1h 0400F2h Port P10_1 Port Function Select Register 0400F3h 0400F4h Port P10_2 Port Function Select Register 0400F5h 0400F6h Port P10_3 Port Function Select Register 0400F7h 0400F8h Port P10_4 Port Function Select Register 0400F9h 0400FAh Port P10_5 Port Function Select Register 0400FBh 0400FCh Port P10_6 Port Function Select Register 0400FDh 0400FEh Port P10_7 Port Function Select Register 0400FFh 040100h 040101h 040102h 040103h 040104h 040105h 040106h 040107h 040108h 040109h 04010Ah 04010Bh 04010Ch 04010Dh 04010Eh 04010Fh 040110h 040111h 040112h 040113h 040114h 040115h 040116h 040117h 040118h 040119h 04011Ah 04011Bh 04011Ch 04011Dh 04011Eh 04011Fh X: Undefined Blanks are reserved. No access is allowed.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 41 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.23
SFR List (23)
Symbol Reset Value
Address Register 040120h to 04403Fh 044040h 044041h 044042h 044043h 044044h 044045h 044046h 044047h 044048h 044049h 04404Ah 04404Bh 04404Ch 04404Dh 04404Eh Watchdog Timer Start Register 04404Fh Watchdog Timer Control Register 044050h 044051h 044052h 044053h 044054h 044055h 044056h 044057h 044058h 044059h 04405Ah 04405Bh 04405Ch 04405Dh 04405Eh 04405Fh Protect Register 2 X: Undefined Blanks are reserved. No access is allowed.
WDTS WDC
XXXX XXXXb 000X XXXXb
PRCR2
0XXX XXXXb
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 42 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
4. Special Function Registers (SFRs)
Table 4.24
SFR List (24)
Symbol Reset Value
Address Register 044060h 044061h 044062h 044063h 044064h 044065h 044066h 044067h 044068h 044069h 04406Ah 04406Bh 04406Ch 04406Dh External Interrupt Source Select Register 1 04406Eh 04406Fh External Interrupt Source Select Register 0 044070h DMA0 Request Source Select Register 2 044071h DMA1 Request Source Select Register 2 044072h DMA2 Request Source Select Register 2 044073h DMA3 Request Source Select Register 2 044074h 044075h 044076h 044077h 044078h DMA0 Request Source Select Register 1 044079h DMA1 Request Source Select Register 1 04407Ah DMA2 Request Source Select Register 1 04407Bh DMA3 Request Source Select Register 1 04407Ch 04407Dh Wake-up/Interrupt Priority Level Control Register 2 04407Eh 04407Fh Wake-up/Interrupt Priority Level Control Register 1 044080h 044081h 044082h 044083h 044084h 044085h 044086h 044087h 044088h 044089h 04408Ah 04408Bh 04408Ch 04408Dh 04408Eh 04408Fh X: Undefined Blanks are reserved. No access is allowed.
IFSR1 IFSR0 DM0SL2 DM1SL2 DM2SL2 DM3SL2
X0XX XXXXb 0000 0000b XX00 0000b XX00 0000b XX00 0000b XX00 0000b
DM0SL DM1SL DM2SL DM3SL RIPL2 RIPL1
XXX0 0000b XXX0 0000b XXX0 0000b XXX0 0000b XX0X 0000b XX0X 0000b
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 43 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
5.
Electrical Characteristics
Absolute Maximum Ratings (1)
Table 5.1
Symbol VCC1, VCC2 Supply voltage VCC2 AVCC VI Supply voltage
Characteristic
Condition VCC1 = AVCC -- VCC1 = AVCC
Value -0.3 to 6.0 -0.3 to VCC1 -0.3 to 6.0
Unit V V V
Analog supply voltage Input voltage XIN, RESET, CNVSS, NSD, VREF, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 P7_0, P7_1
-0.3 to VCC1 +0.3
V
-0.3 to VCC2 +0.3 -0.3 to 6.0 -0.3 to VCC1 +0.3
V V V
VO
Output voltage
XOUT, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7 , P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 P7_0, P7_1
-0.3 to VCC2 +0.3 -0.3 to 6.0 Ta = 25C 500 -40 to 85 -65 to 150
V V mW C C
Pd -- Tstg
Power consumption Operating temperature range Storage temperature range
Note: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 44 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
Table 5.2
Operating Conditions (1) (1)
Symbol VCC1, VCC2 AVCC VREF VSS AVSS VIH
Characteristic Digital supply voltage (VCC1 VCC2) Analog supply voltage Reference voltage Digital ground voltage Analog ground voltage High level P2_0 to P2_7, P3_0 to P3_7, input voltage P4_0 to P4_7, P5_0 to P5_7 XIN, RESET, CNVSS, NSD, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7 (2), P9_1, P9_3 to P9_7, P10_0 to P10_7 P7_0, P7_1 P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode)
Value Min. 3.0 Typ. 5.0
VCC1
Max. 5.5
Unit V V
3.0 0 0 0.8 x VCC2
VCC1
V V V
VCC2
V
0.8 x VCC1
VCC1
V
0.8 x VCC1 0.8 x VCC2
6.0 VCC2 VCC2
V V
P0_0 to P0_7, P1_0 to P1_7 (in memory 0.5 x VCC2 expansion mode or microprocessor mode) VIL Low level P2_0 to P2_7, P3_0 to P3_7, input voltage P4_0 to P4_7, P5_0 to P5_7 XIN, RESET, CNVSS, NSD, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7 (2), P9_1, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode) P0_0 to P0_7, P1_0 to P1_7 (in memory expansion mode or microprocessor mode) Topr Operating Version N temperature Version D range 0
V
0.2 x VCC2
V
0
0.2 x VCC1
V
0
0.2 x VCC2 0.16 x VCC2 85 85
V
0 -20 -40
V C C
Notes: 1. The device is operationally guaranteed under these operating conditions. 2. VIH and VIL for P8_7 are specified for P8_7 as a programmable port. These values are not applicable to P8_7 as XCIN.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 45 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
Table 5.3
Operating Conditions (2) (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol CVDC
Characteristic Decoupling capacitance of voltage regulator Inter-pin voltage: 1.5 V
Value Min. 2.4 Typ. Max. 10.0
Unit F
Note: 1. The device is operationally guaranteed under these operating conditions.
Table 5.4
Operating Conditions (3) (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol IOH(peak) High level peak output current (2) High level average output current (3) Low level peak output current (2) Low level average output current (3)
Characteristic P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
Value Min. Typ. Max.
Unit
-10.0
mA
IOH(avg)
-5.0
mA
IOL(peak)
10.0
mA
IOL(avg)
5.0
mA
Notes: 1. The device is operationally guaranteed under these operating conditions. 2. The following conditions should be satisfied: * The sum of IOL(peak) of pots P0, P1, P2, P8_6, P8_7, P9, P10 is 80 mA or less. * The sum of IOL(peak) of ports P3, P4, P5, P6, P7, P8_0 to P8_4 is 80 mA or less. * The sum of IOH(peak) of ports P0, P1, P2 is -40 mA or less. * The sum of IOH(peak) of ports P8_6, P8_7, P9, P10 is -40 mA or less. * The sum of IOH(peak) of ports P3, P4, P5 is -40 mA or less. * The sum of IOH(peak) of ports P6, P7, and P8_0 to P8_4 is -40 mA or less. 3. Average value within 100 ms.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 46 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
Table 5.5
Operating Conditions (4) (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol f(XIN) f(XRef) f(PLL) f(Base) tc(Base) f(CPU) tc(CPU) f(BCLK) tc(BCLK) f(PER) f(XCIN)
Characteristic Main clock oscillator frequency Reference clock frequency PLL clock oscillator frequency Base clock frequency Base clock cycle time CPU operating frequency CPU clock cycle time Peripheral bus clock operating frequency Peripheral bus clock cycle time Peripheral clock source frequency Sub clock oscillator frequency
Value Min. 4 2 96 Typ. Max. 16 4 128 50 20 50 20 25 40 32 32.768 62.5
Unit MHz MHz MHz MHz ns MHz ns MHz ns MHz kHz
Note: 1. The device is operationally guaranteed under these operating conditions.
t c(Base)
Base clock (Internal signal)
t c(CPU)
CPU clock (Internal signal)
t c(BCLK)
Peripheral bus clock (Internal signal)
Figure 5.1
Clock Cycle Time
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 47 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
Table 5.6
Operating Conditions (5) (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol Vr(VCC) Vr(VCC) Allowable ripple voltage
Characteristic VCC = 5.0 V VCC = 3.0 V Allowable ripple voltage VCC = 5.0 V VCC = 3.0 V VCC = 5.0 V VCC = 3.0 V VCC = 5.0 V VCC = 3.0 V
Value Min. Typ. Max. 0.5 0.3 0.5 0.3 0.3 0.3 0.3 0.3 10 10
Unit Vp-p Vp-p Vp-p Vp-p V/ms V/ms V/ms V/ms kHz kHz
dVr(VCC)/dt Ripple voltage gradient dVr(VCC)/dt Ripple voltage gradient fr(VCC) fr(VCC) Allowable ripple frequency Allowable ripple frequency
Note: 1. The device is operationally guaranteed under these operating conditions.
1 / f r(VCC1)
or
1 / f r(VCC2)
VCC1 or VCC2
Vr(VCC1) or Vr(VCC2)
Figure 5.2
Ripple Waveform
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 48 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
Table 5.7
Flash Memory Electrical Characteristics (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol -- -- --
Characteristic Programming and erasure endurance of flash Program area memory (1) Data area 4-word program time Lock bit-program time Block erasure time Program area Data area Program area Data area 4 Kbyte block 32 Kbyte block 64 Kbyte block Flash memory circuit start-up stabilization time
Value Min. 1000 10000 150 300 70 140 0.12 0.17 0.20 900 1700 500 1000 3.0 3.0 3.0 65 Ta = 55C (3) 10 Typ. Max.
Unit times times s s s s s s s s years
-- tPS --
Data retention (2)
Notes: 1. Program/erase definition This value represents the number of erasures per block. If the flash memory is programmed/erased n times, each block can be erased n times. i.e. If 4-word write is performed in 512 different addresses in the block A of 4 Kbyte and then the block is erased, it is considered the programming/erasure is performed just once. However a write in the same address more than once for one erasure is disabled. (overwrite disabled). 2. The data retention time includes the periods when the supply voltage is not applied and no clock is provided. 3. Please contact a Renesas sales office regarding data retention time other than the above.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 49 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
Table 5.8
Power Supply Circuit Timing Characteristics (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol td(P-R)
Characteristic
Measurement condition
Value Min. Typ. Max. 2
Unit
Internal power supply start-up stabilization VCC1 = 3.0 to 5.5 V time after the main power supply is turned on
ms
t d(P-R) Internal power supply start-up stabilization time after the main power supply is turned on
VCC1
Recommended operating voltage t d(P-R)
PLL oscillatoroutput waveform CPU clock
Figure 5.3
Power Supply Circuit Timing
Table 5.9
Electrical Characteristics of Voltage Regulator for Internal Logic (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol VVDC1
Characteristics Output voltage
Measurement condition
Value Min. Typ. 1.5 Max.
Unit V
Table 5.10
Electrical Characteristics of Low Voltage Detector (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
Vdet
Characteristics Detected voltage error
Measurement condition
Value Min. 0 Typ. Max. TBD
Unit V V
Vdet(R)-Vdet(F) Hysteresis width Self-consuming current -- td(E-A) VCC = 5.0 V, low voltage detector enabled
4 150
A s
Operation start time of low voltage detector
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 50 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
Table 5.11
Electrical Characteristics of Oscillator (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol fSO(PLL) tOSC(PLL) tjitter(p-p) f(OCO)
Characteristics PLL clock self-oscillation frequency PLL frequency synthesizer stabilization time
(1)
Measurement condition
Value Min. 35 Typ. 50 Max. 65 1 2.0 62.5 125 250
Unit MHz ms ns kHz
PLL jitter period (p-p) On-chip oscillator frequency
Note: 1. This value is applicable only when the main clock oscillation is stable.
Table 5.12 Electrical Characteristics of Clock Circuitry (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol trec(STOP) trec(WAIT)
Characteristics Recovery time from stop mode (1)
Measurement condition
Value Min. Typ. Max. 225 225
Unit s s
Recovery time from wait mode to low power mode
Note: 1. This recovery time does not include the period until both the main clock and sub clock oscillators are stabilized. The CPU starts operating before the oscillators are stabilized.
t rec(STOP) Recovery time from stop mode
Interrupt for exiting stop mode Main clock oscillator output On-chip oscillator output CPU clock t rec(STOP)
t rec(WAIT) Recovery time from wait mode to low power mode
Interrupt for exiting wait mode Sub clock oscillator output On-chip oscillator output CPU clock t rec(WAIT)
Figure 5.4
Clock Circuit Timing
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 51 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
Timing Requirements (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.13 Flash Memory CPU Rewrite Mode Timing
Symbol tcR tsu(S-R) th(R-S) tsu(A-R) th(R-A) tw(R) tcW tsu(S-W) th(W-S) tsu(A-W) th(W-A) tw(W) Read cycle time
Characteristics
Value Min. 200 200 0 200 0 100 200 0 30 0 30 50 Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Chip-select setup time for read Chip-select hold time after read Address setup time for read Address hold time after read Read pulse width Write cycle time Chip-select setup time for write Chip-select hold time after write Address setup time for write Address hold time after write Write pulse width
Read cycle
t su(S-R) CS0 t su(A-R) A23 to A0, BC0 to BC3
t cR t h(R-S)
t h(R-A)
t w(R) RD
Write cycle
t su(S-W) CS0 to CS3 t su(A-W) A23 to A0, BC0 to BC3
t cW t h(W-S)
t h(W-A)
t w(W) WR
Figure 5.5
Flash Memory CPU Rewrite Mode Timing
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 52 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.14 Electrical Characteristics (1) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 50 MHz, unless otherwise noted)
Symbol VOH
Characteristic High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to output P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7 , P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7 , P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 , P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7 , P9_3 to P9_7, P10_0 to P10_7
Measurement condition IOH = -5 mA
Value Min. VCC2 -2.0 Typ. Max. VCC2
Unit
V
IOH = -5 mA
VCC1 -2.0
VCC1
V
IOH = -200 A VCC2 -0.3
VCC2
V
IOH = -200 A VCC1 -0.3
VCC1
V
VOL
Low level P0_0 to P0_7, P1_0 to P1_7, output P2_0 to P2_7, P3_0 to P3_7, voltage P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
IOL = 5 mA
2.0
V
IOL=200 A
0.45
V
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 53 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.15 Electrical Characteristics (2) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 50 MHz, unless otherwise noted)
Symbol VT+ - VT- Hysteresis
Characteristic
HOLD, RDY, NMI, INT0 to INT5, KI0 to KI3, TA0IN to TA4IN, TA0OUT to TA4OUT, TB0IN to TB5IN, CTS0 to CTS8, CLK0 to CLK8, RXD0 to RXD8, SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6, SRXD0 to SRXD6, ADTRG, IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A, UD0B, UD1A, UD1B, ISCLK2, ISRXD2, IEIN RESET
Measurement condition
Value Min. Typ. Max.
Unit
0.2
1.0
V
0.2
1.8
V
IIH
High level XIN, RESET, CNVSS, NSD, input current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 Low level XIN, RESET, CNVSS, NSD, input current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 XIN XCIN
VI = 5 V
5.0
A
IIL
VI = 0 V
-5.0
A
RPULLUP Pull-up resistor
VI = 0 V
30
50
170
k
RfXIN RfXCIN
Feedback resistor Feedback resistor
1.5 15
M M
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 54 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.16 Electrical Characteristics (3) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
ICC
Characte ristic
Power supply current
Measurement condition
In single-chip mode, output pins are left open and others are connected to VSS XIN-XOUT Drive power: low XCIN-XCOUT Drive power: low f(CPU) = 50 MHz, f(BCLK) = 25 MHz, f(XIN) = 8 MHz Active: PLL, Stopped: XCIN, OCO f(CPU) = fSO(PLL)/24 MHz, Active: PLL (self-oscillation), Stopped: XIN, XCIN, OCO f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Stopped: PLL, XCIN, OCO f(CPU) = f(BCLK) = 32.768 kHz, Active: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown f(CPU) = f(BCLK) = f(OCO)/4 kHz, Active: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Stopped: XCIN, PLL, OCO, Ta = 25C, Wait mode f(CPU) = f(BCLK) = 32.768 kHz, Active: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown, Ta = 25C, Wait mode f(CPU) = f(BCLK) = f(OCO)/4 kHz, Active: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown, Ta = 25C, Wait mode Stopped: all clocks, Main regulator: shutdown, Ta = 25C Stopped: all clocks, Main regulator: shutdown, Ta = 85C
Value Min. Typ. Max.
32 45
Unit
mA
10
mA
1.2
mA
220
A
230
A
960
1600
A
8
140
A
10
150
A
5
70
A
TBD
A
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 55 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.17 A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 25 MHz, unless otherwise noted)
Symbol --
Characteristic Resolution Absolute error
Measurement condition VREF = VCC1 VREF = VCC1 = VCC2 = AN_0 to AN_7, AN0_0 to AN0_7, 5V AN2_0 to AN2_7, ANEX0, ANEX1 External op-amp connection mode
Value Min. Typ. Max. 10
Unit Bits
3
LSB
--
7
LSB
INL
Integral non-linearity error
VREF = VCC1 = VCC2 = AN_0 to AN_7, AN0_0 to AN0_7, 5V AN2_0 to AN2_7, ANEX0, ANEX1 External op-amp connection mode
3
LSB
7 1 3 3
LSB LSB LSB LSB k s s s s s
DNL -- -- tCONV
Differential non-linearity error Offset error Gain error VREF = VCC1
AD = 16 MHz, with sample & hold function AD = 16 MHz, without sample & hold function
RLADDER Resistor ladder Conversion time (10 bits)
4 2.06 3.69 1.75 3.06 0.188 0
20
tCONV
Conversion time (8 bits)
AD = 16 MHz, with sample & hold function AD = 16 MHz, without sample & hold function
tSAMP VIA
AD
Sample time Analog input voltage Operating clock frequency
AD = 16 MHz
VREF 16 16
V MHz MHz
without sample & hold function with sample & hold function
0.125 1
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 56 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.18 D/A Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol -- -- tS RO IVREF
Characteristic Resolution Absolute precision Settling time Output resistance Reference input current
Measurement condition
Value Min. Typ. Max. 8 1.0 3 4 10 20 1.5
Unit Bits % s k mA
(1)
Note: 1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for A/D converter is not considered. Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 57 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.19 External Clock Input
Symbol tc(X) tw(XH) tw(XL) tr(X) tf(X) tw / tc External clock input period
Characteristic
Value Min. 62.5 25 25 5 5 40 60 Max. 250
Unit ns ns ns ns ns %
External clock input high level pulse width External clock input low level pulse width External clock input rise time External clock input fall time External clock input duty
Table 5.20
External Bus Timing
Symbol tsu(D-R) th(R-D) tdis(R-D) Data setup time for read
Characteristic
Value Min. TBD TBD TBD Max.
Unit ns ns ns
Data hold time after read Data disable time after read
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 58 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.21 Timer A Input (Counting input in event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.22
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Timer A Input (Gating input in timer mode)
Value Min. 200 80 80 Max.
Unit ns ns ns
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.23
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Timer A Input (External trigger input in one-shot timer mode)
Value Min. 400 180 180 Max.
Unit ns ns ns
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.24
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Value Min. 200 80 80 Max.
Unit ns ns ns
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol tw(TAH) tw(TAL)
Table 5.25
Characteristic TAiIN input high level pulse width TAiIN input low level pulse width
Value Min. 80 80 Max.
Unit ns ns
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP)
Characteristic TAiOUT input clock period TAiOUT input high level pulse width TAiOUT input low level pulse width TAiOUT input setup time TAiOUT input hold time
Value Min. 2000 1000 1000 400 400 Max.
Unit ns ns ns ns ns
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 59 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.26 Timer B Input (Counting input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Table 5.27
Characteristic TBiIN input clock period (one edge counting) TBiIN input high level pulse width (one edge counting) TBiIN input low level pulse width (one edge counting) TBiIN input clock period (both edges counting) TBiIN input high level pulse width (both edges counting) TBiIN input low level pulse width (both edges counting)
Timer B Input (Pulse period measure mode)
Value Min. 200 80 80 200 80 80 Max.
Unit ns ns ns ns ns ns
Symbol tc(TB) tw(TBH) tw(TBL)
Table 5.28
Characteristic TBiIN input clock period TBiIN input high level pulse width TBiIN input low level pulse width
Timer B Input (Pulse-width measure mode)
Value Min. 400 180 180 Max.
Unit ns ns ns
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input clock period
Characteristic
Value Min. 400 180 180 Max.
Unit ns ns ns
TBiIN input high level pulse width TBiIN input low level pulse width
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 60 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Timing requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.29 Serial Interface
Symbol tc(CK) tw(CKH) tw(CKL) tsu(D-C) th(C-Q) CLKi input clock period
Characteristic
Value Min. 200 80 80 30 90 Max.
Unit ns ns ns ns ns
CLKi input high level pulse width CLKi input low level pulse width RXDi input setup time RXDi input hold time
Table 5.30
A/D Trigger Input
Symbol tw(ADH) tw(ADL)
Characteristic
ADTRG input high level pulse width Hardware trigger input high level pulse width ADTRG input low level pulse width Hardware trigger input high level pulse width
Value Min.
2----------AD
Max.
Unit ns ns
125
Table 5.31
External Interrupt INTi Input
Symbol tw(INH)
Characteristic
INTi input high level pulse width INTi input low level pulse width
Value Min. Edge sensitive Level sensitive 250 tc(CPU) + 200 250 tc(CPU) + 200 Max.
Unit ns ns ns ns
tw(INL)
Edge sensitive Level sensitive
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 61 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.32 External Bus Timing (Separate bus)
Symbol tsu(S-R) th(R-S) tsu(A-R) th(R-A) tw(R) tsu(S-W) th(W-S) tsu(A-W) th(W-A) tw(W) tsu(D-W) th(W-D)
Characteristic Chip-select setup time for read Chip-select hold time after read Address setup time for read Address hold time after read Read pulse width Chip-select setup time for write Chip-select hold time after write Address setup time for write Address hold time after write Write pulse width Data setup time for write Data hold time after write
Measurement condition
Value Min.
(1)
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tc(Base) - 10
(1)
tc(Base) - 10
(1)
Refer to Figure 5.6
(1)
1.5 x tc(Base) - 10
(1)
1.5 x tc(Base) - 10
(1) (1)
0
Note: 1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the Hardware manual. tsu(S-R) = tsu(A-R) = Tsu(A-R) x tc(Base) - 15 [ns] tw(R) = Tw(R) x tc(Base) - 10 [ns] tsu(S-W) = tsu(A-W) = Tsu(A-W) x tc(Base) - 10 [ns] tw(W) = tsu(D-W) = Tw(W) x tc(Base) - 10 [ns]
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 62 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and unless otherwise noted) Table 5.33 External Bus Timing (Multiplexed bus)
Symbol tsu(S-ALE) th(R-S) tsu(A-ALE) th(ALE-A) th(R-A) td(ALE-R) tw(ALE) tdis(R-A) tw(R) th(W-S) th(W-A) td(ALE-W) tw(W) tsu(D-W) th(W-D)
Characteristic Chip-select hold time for ALE Chip-select hold time after read Address setup time for ALE Address hold time after ALE Address hold time after read ALE-read delay time ALE pulse width Address disable time after read Read pulse width Chip-select hold time after write Address hold time after write ALE-write delay time Write pulse width Data setup time for write Data hold time after write
Measurement condition
Value Min.
(1)
Max.
Unit ns ns ns ns ns
1.5 x tc(Base) - 10
(1)
0.5 x tc(Base) - 5 1.5 x tc(Base) - 10
(1)
0.5 x tc(Base) - 5 0.5 x tc(Base) + 10 ns ns 8
(1)
Refer to Figure 5.6 1.5 x tc(Base) - 10 1.5 x tc(Base) - 10
(1) (1)
ns ns ns ns
0.5 x tc(Base) - 5 0.5 x tc(Base) + 10 ns ns ns ns
0
Note: 1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the Hardware manual. tsu(S-ALE) = tsu(A-ALE) = tw(ALE) = Tsu(A-R) x tc(Base) -15 [ns] tw(R) = Tw(R) x tc(Base) -10 [ns] tw(W) = tsu(D-W) = Tw(W) x tc(Base) -10 [ns]
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 63 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.34 Serial Interface
Symbol td(C-Q) th(C-Q)
Characteristic TXDi output delay time TXDi hold time
Measurement condition Refer to Figure 5.6
Value Min. Max. 80 0
Unit ns ns
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 64 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.35 Electrical Characteristics (1) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and f(CPU) = 50 MHz, unless otherwise noted)
Symbol VOH
Characteristic High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to output P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7 , P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7 , P9_3 to P9_7, P10_0 to P10_7
Measurement condition IOH = -1 mA
Value Min. VCC2 -0.6 Typ. Max. VCC2
Unit
V
IOH = -1 mA
VCC1 -0.6
VCC1
V
VOL
Low level P0_0 to P0_7, P1_0 to P1_7, output P2_0 to P2_7, P3_0 to P3_7, voltage P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_3 to P9_7, P10_0 to P10_7
IOL = 1 mA
0.5
V
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 65 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.36 Electrical Characteristics (2) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and f(CPU) = 50 MHz, unless otherwise noted)
Symbol
Characteristic
Measurement condition
Value Min. Typ. Max.
Unit
VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT5, KI0 to KI3, TA0IN to TA4IN, TA0OUT to TA4OUT, TB0IN to TB5IN, CTS0 to CTS8, CLK0 to CLK8, RXD0 to RXD8, SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6, SRXD0 to SRXD6, ADTRG, IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A, UD0B, UD1A, UD1B, ISCLK2, ISRXD2, IEIN
RESET
0.2
1.0
V
0.2
1.8
V
IIH
High level XIN, RESET, CNVSS, NSD, input P0_0 to P0_7, P1_0 to P1_7, current P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 Low level XIN, RESET, CNVSS, NSD, input P0_0 to P0_7, P1_0 to P1_7, current P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_1, P9_3 to P9_7, P10_0 to P10_7
VI = 3 V
4.0
A
IIL
VI= 0 V
-4.0
A
RPULLUP Pull-up resistor
VI = 0 V
50
100
500
k
RfXIN RfXCIN
Feedback XIN resistor Feedback XCIN resistor
3 25
M M
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 66 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.37 Electrical Characteristics (3) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
ICC
Characte ristic
Power supply current In single-chip mode, output pins are left open and others are connected to VSS XIN-XOUT Drive power: low XCIN-XCOUT Drive power: low
Measurement condition
f(CPU) = 50 MHz, f(BCLK) = 25 MHz, f(XIN) = 8 MHz Active: PLL, Stopped: XCIN, OCO f(CPU) = fSO(PLL)/24 MHz, Active: PLL (self-oscillation), Stopped: XIN, XCIN, OCO f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Stopped: PLL, XCIN, OCO f(CPU) = f(BCLK) = 32.768 kHz, Active: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown f(CPU) = f(BCLK) = f(OCO)/4 kHz, Active: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Stopped: PLL, XCIN, OCO, Ta = 25C, Wait mode f(CPU) = f(BCLK) = 32.768 kHz, Active: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown, Ta = 25C, Wait mode f(CPU) = f(BCLK) = f(OCO)/4 kHz, Active: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown, Ta = 25C, Wait mode Stopped: all clocks, Main regulator: shutdown, Ta = 25C Stopped: all clocks, Main regulator: shutdown, Ta = 85C
Value Min. Typ. Max.
Unit
28
40
mA
7
mA
670
A
180
A
190
A
500
900
A
8
140
A
10
150
A
5
70
A
TBD
A
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 67 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.38 A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 25 MHz, unless otherwise noted)
Symbol --
Characteristic Resolution Absolute error
Measurement condition VREF = VCC1 VREF = VCC1 = VCC2 = AN_0 to AN_7, AN0_0 to AN0_7, 3.3 V AN2_0 to AN2_7, ANEX0, ANEX1 External op-amp connection mode
Value Min. Typ. Max. 10
Unit Bits
5
LSB
--
7
LSB
INL
Integral non-linearity error
VREF = VCC1 = VCC2 = AN_0 to AN_7, AN0_0 to AN0_7, 3.3 V AN2_0 to AN2_7, ANEX0, ANEX1 External op-amp connection mode
5
LSB
7 1 3 3
LSB LSB LSB LSB k s s s
DNL -- -- tCONV tCONV tSAMP VIA
AD
Differential non-linearity VREF = VCC1 = VCC2 = 3.3 V Offset error Gain error VREF = VCC1
AD = 10 MHz, with sample & hold function AD = 10 MHz, with sample & hold function AD = 10 MHz
RLADDER Resistor ladder Conversion time (10 bits) Conversion time (8 bits) Sampling time Analog input voltage Operating clock frequency
4 3.3 2.8 0.3 0
20
VREF 10 10
V MHz MHz
without sample & hold function with sample & hold function
0.125 1
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 68 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.39 D/A Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol -- -- tS RO IVREF
Characteristic Resolution Absolute precision Settling time Output resistance Reference input current
Measurement condition Min.
Value Typ. Max. 8 1.0 3 4 10 20 1.0
Unit Bits % s k mA
(1)
Note: 1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for A/D converter is not considered. Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 69 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.40 External Clock Input
Symbol tc(X) tw(H) tw(L) tr tf tw / tc
Characteristic External clock input period External clock input high level pulse width External clock input low level pulse width External clock input rise time External clock input fall time External clock input duty
Value Min. 62.5 25 25 5 5 40 60 Max. 250
Unit ns ns ns ns ns %
Table 5.41
External Bus Timing
Symbol tsu(D-R) th(R-D) tdis(R-D) Data setup time for read
Characteristic
Value Min. TBD TBD TBD Max.
Unit ns ns ns
Data hold time after read Data disable time after read
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 70 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.42 Timer A Input (Counting input in event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.43
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Timer A Input (Gating input in timer mode)
Value Min. 200 80 80 Max.
Unit ns ns ns
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.44
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Timer A Input (External trigger input in one-shot timer mode)
Value Min. 400 180 180 Max.
Unit ns ns ns
Symbol tc(TA) tw(TAH) tw(TAL)
Table 5.45
Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width
Value Min. 200 80 80 Max.
Unit ns ns ns
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol tw(TAH) tw(TAL)
Table 5.46
Characteristic TAiIN input high level pulse width TAiIN input low level pulse width
Value Min. 80 80 Max.
Unit ns ns
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP)
Characteristic TAiOUT input clock period TAiOUT input high level pulse width TAiOUT input low level pulse width TAiOUT input setup time TAiOUT input hold time
Value Min. 2000 1000 1000 400 400 Max.
Unit ns ns ns ns ns
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 71 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.47 Timer B Input (Counting input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Table 5.48
Characteristic TBiIN input clock period (one edge counting) TBiIN input high level pulse width (one edge counting) TBiIN input low level pulse width (one edge counting) TBiIN input clock period (both edges counting) TBiIN input high level pulse width (both edges counting) TBiIN input low level pulse width (both edges counting)
Timer B Input (Pulse period measure mode)
Value Min. 200 80 80 200 80 80 Max.
Unit ns ns ns ns ns ns
Symbol tc(TB) tw(TBH) tw(TBL)
Table 5.49
Characteristic TBiIN input clock period TBiIN input high level pulse width TBiIN input low level pulse width
Timer B Input (Pulse-width measure mode)
Value Min. 400 180 180 Max.
Unit ns ns ns
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input clock period
Characteristic
Value Min. 400 180 180 Max.
Unit ns ns ns
TBiIN input high level pulse width TBiIN input low level pulse width
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 72 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.50 Serial Interface
Symbol tc(CK) tw(CKH) tw(CKL) tsu(D-C) th(C-D) CLKi input clock period
Characteristic
Value Min. 200 80 80 30 90 Max.
Unit ns ns ns ns ns
CLKi input high level pulse width CLKi input low level pulse width RXDi input setup time RXDi input hold time
Table 5.51
A/D Trigger Input
Symbol tw(ADH) tw(ADL)
Characteristic
ADTRG input high level pulse width Hardware trigger input high pulse width ADTRG input low level pulse width Hardware trigger input high pulse width
Value Min.
2----------AD
Max.
Unit ns ns
125
Table 5.52
External Interrupt INTi Input
Symbol tw(INH)
Characteristic
INTi input high level pulse width INTi input low level pulse width
Value Min. Edge sensitive Level sensitive 250 tc(CPU) + 200 250 tc(CPU) + 200 Max.
Unit ns ns ns ns
tw(INL)
Edge sensitive Level sensitive
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 73 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.53 External Bus Timing (Separate bus)
Symbol tsu(S-R) th(R-S) tsu(A-R) th(R-A) tw(R) tsu(S-W) th(W-S) tsu(A-W) th(W-A) tw(W) tsu(D-W) th(W-D)
Characteristic Chip-select setup time for read Chip-select hold time after read Address setup time for read Address hold time after read Read pulse width Chip-select setup time for write Chip-select hold time after write Address setup time for write Address hold time after write Write pulse width Data setup time for write Data hold time after write
Measurement condition
Value Min.
(1)
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tc(Base) - 10
(1)
tc(Base) - 10
(1) (1)
Refer to Figure 5.6
1.5 x tc(Base) - 10
(1)
1.5 x tc(Base) - 10
(1) (1)
0
Note: 1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the Hardware manual. tsu(S-R) = tsu(A-R) = Tsu(A-R) x tc(Base) - 15 [ns] tw(R) = Tw(R) x tc(Base) - 10 [ns] tsu(S-W) = tsu(A-W) = Tsu(A-W) x tc(Base) - 10 [ns] tw(W) = tsu(D-W) = Tw(W) x tc(Base) - 10 [ns]
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 74 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.54 External Bus Timing (Multiplexed bus)
Symbol tsu(S-ALE) th(R-S) tsu(A-ALE) th(ALE-A) th(R-A) td(ALE-R) tw(ALE) tdis(R-A) tw(R) th(W-S) th(W-A) td(ALE-W) tw(W) tsu(D-W) th(W-D)
Characteristic Chip-select hold time after ALE Chip-select hold time after read Address setup time for ALE Address hold time after ALE Address hold time after read ALE-read delay time ALE pulse width Address disable time after read Read pulse width Chip-select hold time after write Address hold time after write ALE-write delay time Write pulse width Data setup time for write Data hold time after write
Measurement condition
Value Min.
(1)
Max.
Unit ns ns ns ns ns
1.5 x tc(Base) - 10
(1)
0.5 x tc(Base) - 5 1.5 x tc(Base) - 10
0.5 x tc(Base) - 5 0.5 x tc(Base) + 10 ns
(1)
ns 8 ns ns ns ns
Refer to Figure 5.6
(1)
1.5 x tc(Base) - 10 1.5 x tc(Base) - 10
(1) (1)
0.5 x tc(Base) - 5 0.5 x tc(Base) + 10 ns ns ns ns
0
Note: 1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the Hardware manual. tsu(S-ALE) = tsu(A-ALE) = tw(ALE) = Tsu(A-R) x tc(Base) -15 [ns] tw(R) = Tw(R) x tc(Base) -10 [ns] tw(W) = tsu(D-W) = Tw(W) x tc(Base) -10 [ns]
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 75 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.55 Serial Interface
Symbol td(C-Q) th(C-Q)
Characteristic TXDi output delay time TXDi hold time
Measurement condition Refer to Figure 5.6
Value Min. Max. 80 0
Unit ns ns
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 76 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
MCU
Pin to be measured
30 pF
Figure 5.6
Switching Characteristic Measurement Circuit
t c(X)
XIN
t w(XH) t r(X) t f(X) t w(XL)
Figure 5.7
External Clock Input Timing
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 77 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
External bus timing (Separate bus) Read cycle
t su(S-R) CS0 to CS3 t su(A-R) A23 to A0, BC0 and BC1 t w(R) RD t su(D-R) D15 to D0 t h(R-D) t h(R-A)
t cR t h(R-S)
Write cycle
t su(S-W) CS0 to CS3 t su(A-W) A23 to A0, BC0 and BC1
t cW t h(W-S)
t h(W-A)
t w(W) WR, WR0 and WR1 t su(D-W) D15 to D0 t h(W-D)
Measurement conditions Item Criterion for input voltage Criterion for output voltage VIH VIL VOH VOL VCC1 = VCC2 = 4.2 to 5.5 V 2.5 V 0.8 V 2.0 V 0.8 V VCC1 = VCC2 = 3.0 to 3.6 V 1.5 V 0.5 V 2.4 V 0.5 V
Figure 5.8
External Bus Timing (Separate Bus)
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 78 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
External bus timing (Multiplexed bus) Read cycle
t su(S-ALE) CS0 to CS3 t su(A-ALE) A23 to A8, BC0 and BC1 t w(ALE) ALE t su(A-ALE) A15/D15 to A0/D0, BC0/D0 Address t d(ALE-R) RD t su(D-R) D15 to D8 t h(R-D) t w(R) t dis(R-A) t su(D-R) Data t dis(R-D) t h(R-D) t h(ALE-A) t h(R-A) t cR t h(R-S)
Write cycle
t su(S-ALE) CS0 to CS3 t su(A-ALE) A23 to A8, BC0 and BC1 t w(ALE) ALE t su(A-ALE) A15/D15 to A0/D0, BC0/D0 t h(ALE-A)
t cW t h(W-S)
t h(W-A)
t su(D-W) Data t w(W)
t h(W-D)
Address t d(ALE-W)
WR, WR0 and WR1 t su(D-W) D15 to D8 t h(W-D)
Measurement conditions Item Criterion for input voltage Criterion for output voltage VIH VIL VOH VOL VCC1 = VCC2 = 4.2 to 5.5 V 2.5 V 0.8 V 2.0 V 0.8 V VCC1 = VCC2 = 3.0 to 3.6 V 1.5 V 0.5 V 2.4 V 0.5 V
Figure 5.9
External Bus Timing (Multiplexed Bus)
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 79 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
5. Electrical Characteristics
t c(TA) t w(TAH) TAiIN input t c(UP) t w(UPH) TAiOUT input t w(UPL) t w(TAL)
In event counter mode TAiOUT input (input for increment/ decrement count switching) t su(UP-TIN) TAiIN input (in falling edge counting) t h(TIN-UP)
TAiIN input (in rising edge counting) t c(TB) t w(TBH) TBiIN input t c(CK) t w(CKH) CLKi t d(C-Q) TXDi t su(D-C) RXDi t h(C-D) t h(C-Q) t w(CKL) t w(TBL)
t w(ADL) ADTRG input
t w(ADH)
t w(INL) INTi input
t w(INH)
2 CPU clock cycles + 300 ns or more NMI input
2 CPU clock cycles + 300 ns or more
Figure 5.10
Timing of Peripheral Functions
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 80 of 81
Under development
Preliminary Specification This is a preliminary specification and is subject to change.
R32C/111 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g
HD *1 D
75
51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
76
50
bp b1
HE
E
Reference Symbol
*2
Dimension in Millimeters
c1
c
Terminal cross section
1 Index mark ZD
25 F
ZE
100
26
A2
A
D E A2 HD HE A A1 bp b1 c c1
c
A1
y e
*3
bp
L L1 Detail F
x
e x y ZD ZE L L1
Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0
REJ03B0227-0030 Rev.0.30 Aug 19, 2008 Page 81 of 81
REVISION HISTORY
Rev. 0.03 0.30 Date Oct 17, 2007 Aug 19, 2008 Page -- -- --
R32C/111 Group Datasheet
Description Summary Initial release Second edition released The manual in general * Maximum operating frequency changed from 48 MHz to 50 MHz * Specification of on-chip oscillator disclosed * Microprocessor mode becomes optional * "memory-expanded mode" changed to "memory expansion mode" Chapter 1 * "(MCUs)" added to line 1 of 1.1 * Applications in 1.1.1 revised and modified * "Attention Users" below 1.1.1 modified to "Notes to users"; "The specification" in this box changed to "Specifications" * "instructions" in "CPU" of Table 1.1 deleted * Minimum instruction execution time in "CPU" of Table 1.1 changed * Microprocessor mode in CPU" of Table 1.1 changed to optional * "TBD" for "Voltage Detection" in Table 1.1 deleted * "3 circuits" for "Clock" in Table 1.1 changed to "4 circuits" * "Total interrupt vectors" in Table 1.1 changed to "Interrupt vectors" * Trigger sources" for DMA in Table 1.1 modified to "Request sources"; Request sources for "DMA" defined as 51 * Scribal error: "peripheral interrupt sources" for "DMACII" in Table 1.1 corrected to "peripheral interrupt source" * Unit names in Table 1.2 sorted in chapter order * Description for "A/D Converter" in Table 1.2 changed * "Operating frequency" in Table 1.2 changed from "48 MHz" to "50 MHz" * "version N" and "version D" added to "Operating Temperature" in Table 1.2; "optional" deleted * Values for "Current Consumption" in Table 1.2 added * "version N" and "version D" added to Table 1.3 * All "version N"s in Table 1.3 become on planning phase * Figure 1.2 modified * Note 2 for Figure 1.3 modified * Scribal error: "CLK5/" (pin No. 21) in Table 1.4 corrected to "CLK5" * Description for "Connecting pins for decoupling capacitor", "CNVSS", and "Debug port" in Table 1.7 modified * Some descriptions for "WR0/WR1/WR/BC0/BC1/RD" of "Bus control pins" in Table 1.8 modified * Functional category items in Tables 1.9 and 1.10 sorted in chapter order; Descriptions modified
1
2
3
4 6 7 8 11 12 13, 14
A- 1
REVISION HISTORY
Rev. Date Page -- 15 15, 16 18 19 20
R32C/111 Group Datasheet
Description Summary Chapter 2 * Descriptions for this chapter modified; Expression "DMAC-related registers"s modified to "DMAC-associated registers"s * "Data register" and "Address register" in Figure 2.1 pluralized; Explanation in Notes 1 and 2 for this figure revised * "Interrupt table register" in Figure 2.1 and 2.1.6 changed to "Interrupt vector table base register" * Scribal error: "24 bit" in 2.2.2 corrected to "32 bit" Chapter 3 * Descriptions for this chapter and Figure 3.1 modified Chapter 4 * "(SFR)" of chapter title changed to "(SFRs)" * Description for initial paragraph of Chapter 4 modified * Reset value for CCR and PBC in Table 4.1 changed * "UARTi Bus Collision Detection Interrupt Control Register" (i = 0 to 6) in Tables 4.2 and 4.3 changed to "UARTi Bus Collision, Start/Stop Condition Detection Interrupt Control Register" * "DMAi interrupt" in Tables 4.2 and 4.3 changed to "DMAi transfer complete interrupt" * Reset value for IIO3IR and IIO8IR to IIO11R in Table 4.3 modified * Scribal error: address "00010Fh" added to Table 4.6 * "Upward/Downward Counting Select Register" in Table 4.13 changed to "Increment/Decrement Counting Select Register" * CSOP2 for address 040056h in Table 4.19 deleted * Reset value for CM3 in Table 4.19 changed * "DMAi Source Select Register i" in Table 4.24 changed to "DMAi Request Source Select Register i" Chapter 5 * This chapter newly added Appendix 1 * "Package Dimension" as title changed to "Package Dimensions"
21, 22
22 25 32 38 43
-- 81
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